AD8150_15 Datasheet, PDF (22/44 Pages) Analog Devices – Crosspoint Switch

AD8150
RE Input
Second-rank read enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address
with the A[4:0] pins and forcing RE to logic low, the 7-bit data
stored in the second-rank latch for that output address will be
written to the D[6:0] pins. Data should not be written to the
D[6:0] pins externally while in readback mode. The RE and WE
pins are not exclusive and may be used at the same time, but
data should not be written to the D[6:0] pins from external
sources while in readback mode.
CS Input
Chip select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described below. This pin has no effect on the
signal pairs and does not alter any of the stored control data.
RESET Input
Global output disable pin. Forcing the RESET pin to logic low
will reset the enable bit, D6, in all 17 second-rank latches,
regardless of the state of any other pins. This has the effect of
immediately disabling the 17 output signal pairs in the matrix.
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8150 in a system that has multiple output
signal pairs connected together. Failure to do this may result in
several signal outputs contending after power-up. The reset pin
is not gated by the state of the chip-select pin, CS. It should be
noted that the RESET pin does not program the first rank,
which will contain undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8150 control interface has two supply pins, VDD and VSS.
The potential between the positive logic supply VDD and the
negative logic supply VSS must be at least 3 V and no more than
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above VSS, allowing the interface to be used with most
CMOS and TTL logic drivers.
The signal matrix supplies, VCC and VEE, can be set independent
of the voltage on VDD and VSS, with the constraints that (VDD −
VEE) ≤ 10 V. These constraints will allow operation of the
control interface on 3 V or 5 V while the signal matrix is
operated on 3.3 V or 5 V PECL, or on −3.3 V or −5 V ECL.
Rev. A | Page 22 of 44