AD7476A_15 Datasheet, PDF (22/29 Pages) Analog Devices – 2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70

AD7476A/AD7477A/AD7478A
SERIAL INTERFACE
Figure 24, Figure 25, and Figure 26 show the detailed timing
diagrams for serial interfacing to the AD7476A, AD7477A, and
AD7478A, respectively. The serial clock provides the conversion
clock and also controls the transfer of information from the
AD7476A/AD7477A/AD7478A during conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
and takes the bus out of three-state; the analog input is sampled
at this point. Also, the conversion is initiated at this point.
For the AD7476A, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 24 at Point B. On the 16th SCLK falling edge,
the SDATA line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, the conversion is
terminated and the SDATA line goes back into three-state;
otherwise, SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 24. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7476A.
For the AD7477A, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next rising edge as shown
at Point B in Figure 25. If the rising edge of CS occurs before
14 SCLKs have elapsed, the conversion is terminated and the
SDATA line goes back into three-state. If 16 SCLKs are
considered in the cycle, SDATA returns to three-state on the
16th SCLK falling edge, as shown in Figure 25.
For the AD7478A, the conversion requires 12 SCLK cycles to
complete. The track-and-hold goes back into track on the rising
edge after the 11th falling edge, as shown in Figure 26 at Point B. If
the rising edge of CS occurs before 12 SCLKs have elapsed, the
conversion is terminated and the SDATA line goes back into three-
state. If 16 SCLKs are considered in the cycle, SDATA returns to
three-state on the 16th SCLK falling edge, as shown in Figure 26.
t₁
CS
SCLK
t_CONVERT
t₂
t₆
1
2
3
4
5
SDATA
THREE-
STATE
t₃
Z ZERO
ZERO
t₄
ZERO
4 LEADING ZEROS
DB11
t₇
DB10
B
13
14
t₅
15
16
t₈
DB2
DB1
DB0
t_QUIET
THREE-STATE
1/THROUGHPUT
Figure 24. AD7476A Serial Interface Timing Diagram
t₁
CS
SCLK
SDATA
THREE-STATE
t_CONVERT
t₂
t₆
1
2
3
4
5
t₃
Z ZERO
ZERO
ZERO
4 LEADING ZEROS
t₄
DB9
t₇
DB8
B
13
14
t₅
15
16
t₈
t_QUIET
DB0
ZERO
ZERO
2 TRAILING ZEROS
1/ THROUGHPUT
THREE-STATE
Figure 25. AD7477A Serial Interface Timing Diagram
t₁
CS
SCLK
t₂
1
t_CONVERT
t₆
2
3
SDATA
THREE-STATE
t₃
Z ZERO
ZERO
ZERO
4 LEADING ZEROS
4
t₄
DB7
B
11
12
13
14
15
16
t₅
t₈
t₇
ZERO ZERO ZERO
ZERO
4 TRAILING ZEROS
1/ THROUGHPUT
t_QUIET
THREE-STATE
Figure 26. AD7478A Serial Interface Timing Diagram
Rev. F | Page 21 of 28