AD5791ARUZ Datasheet, PDF (22/28 Pages) Analog Devices – 1 ppm 20-Bit, ±1 LSB INL, Voltage Output DAC

AD5791
Data Sheet
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5791 can be reset to its power-on state by two means:
either by asserting the RESET pin or by utilizing the software
RESET control function (see Table 14). If the RESET pin is not
used, it should be hardwired to IOVCC.
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to
be cleared to a user defined value. The 20-bit clear code value
is programmed to the clearcode register (see Table 13). It is
necessary to maintain CLR low for a minimum amount of time
to complete the operation (see Figure 2).When the CLR signal
is returned high the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see Table 14).
Table 9. Hardware Control Pins Truth Table
LDAC CLR RESET Function
X¹
X¹
0
X
X¹
X¹
X
The AD5791 is in reset mode. The device cannot be programmed.
The AD5791 is returned to its power-on state. All registers are set to their default values.
0
0
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
0
1
1
The output is set according to the DAC register value.
1
0
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
1
1
The output is set according to the DAC register value.
0
1
The output remains at the clear code value.
1
1
The output remains set according to the DAC register value.
0
1
The output remains at the clear code value.
1
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
0
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
1
1
The output remains at the clear code value
0
1
The output is set according to the DAC register value.
1 _{X is don’t care.}
ON-CHIP REGISTERS
DAC Register
Table 10 outlines how data is written to and read from the DAC register.
Table 10. DAC Register
MSB
DB23
DB22
R/W
R/W
0
DB21
Register address
0
DB20
1
The following equation describes the ideal transfer function of the DAC:
( ) _{VOUT =}
V_REFP −V_REFN
2²⁰ − 1
× D _{+ VREFN}
where:
VREFN is the negative voltage applied at the VREFN input pins.
VREFP is the positive voltage applied at the VREFP input pins.
D is the 20-bit code programmed to the DAC.
LSB
DB19
DB0
DAC register data
20-bits of data
Rev. C | Page 22 of 28