AD5744R Datasheet, PDF (22/32 Pages) Analog Devices – Complete Quad, 14-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC

AD5744R
V_REFIN
14-BIT
DAC
OUTPUT
I/V AMPLIFIER
V_OUT
LDAC
DAC
REGISTER
INPUT
REGISTER
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
Figure 37. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
TRANSFER FUNCTION
Table 6 shows the ideal input code to output voltage
relationship for the AD5744R for both offset binary and twos
complement data coding.
Table 6. Ideal Output Voltage to Input Code Relationship for
the AD5744R
Digital Input
Analog Output
Offset Binary Data Coding
MSB
LSB
11 1111 1111 1111
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
Twos Complement Data Coding
VOUT
+2 VREF × (8191/8192)
+2 VREF × (1/8192)
0V
−2 VREF × (1/8192)
−2 VREF × (8191/8192)
MSB
01 1111 1111
00 0000 0000
00 0000 0000
11 1111 1111
10 0000 0000
LSB
1111
0001
0000
1111
0000
VOUT
+2 VREF × (8191/8192)
+2 VREF × (1/8192)
0V
−2 VREF × (1/8192)
−2 VREF × (8191/8192)
Preliminary Technical Data
The output voltage expression for the AD5744R is given by
V_OUT
= −2 × V_REFIN
+
4
×
V_REFIN
⎡D
⎢⎣₁₆₃₈₄
⎤
⎥⎦
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFAB/REFCD
pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see Figure 3) for the
operation to complete. When the CLR signal is returned high,
the output remains at the cleared value until a new value is
programmed. If at power-on CLR is at 0 V, then all DAC
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
to the AD5744R.
Rev. PrA | Page 22 of 32