AD5308_1 Datasheet, PDF (22/24 Pages) Analog Devices – 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

AD5308/AD5318/AD5328
POWER
SCLK
SYNC
DIN
5V
REGULATOR
10μF
0.1μF
V_DD
10kΩ
V_DD
10kΩ
V_DD
10kΩ
SCLK
V_DD
V_REFABCD
V_REFEFGH
AD5308/AD5318/
AD5328
SYNC
DIN
GND
V_OUTA
V_OUTB
V_OUTC
V_OUTD
V_OUTE
V_OUTF
V_OUTG
V_OUTH
Figure 42. AD5308/AD5318/AD5328 in an Opto-Isolated Interface
DECODING MULTIPLE AD5308/AD5318/AD5328s
The SYNC pin on the AD5308/AD5318/AD5328 can be used in
applications to decode a number of DACs. In this application,
the DACs in the system receive the same serial clock and serial
data but only the SYNC to one of the devices is active at any one
time, allowing access to four channels in this 16-channel sys-
tem. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded-address inputs are changing state.
Figure 43 shows a diagram of a typical setup for decoding
multiple AD5308 devices in a system.
SCLK
DIN
ENABLE
CODED
ADDRESS
V_DD
V_CC
1G
1Y0
74HC139 _1Y1
1A
1Y2
1B
1Y3
DGND
V_OUTA
V_OUTB
SYNC
AD5308
DIN
SCLK
V_OUTG
V_OUTH
V_OUTA
V_OUTB
SYNC
AD5308
DIN
SCLK
V_OUTG
V_OUTH
V_OUTA
V_OUTB
SYNC
AD5308
DIN
SCLK
V_OUTG
V_OUTH
V_OUTA
V_OUTB
SYNC
AD5308
DIN
SCLK
V_OUTG
V_OUTH
Figure 43. Decoding Multiple AD5308 Devices in a System
Rev. D | Page 22 of 24