SSM3515 Datasheet, PDF (21/41 Pages) Analog Devices – 31 W, Filterless, Class-D Digital Input Audio Amplifier

Data Sheet
DIGITAL AUDIO SERIAL INTERFACE
The SSM3515 includes a standard serial audio interface that is
slave only. The interface is capable of receiving I²S, left justified,
PCM, or TDM formatted data.
The serial interface has three main operating modes, listed in
Table 12.
Table 12. Operating Modes
Mode
Format
2-Channel (Stereo) I²S/left justified
Multichannel TDM I²S/left justified
Comments
Register control
using I²C port
Register control
using I²C port
Stereo modes, typically I²S or left justified, are used when there
is one or two devices on the interface bus. Standard multi-
channel TDM modes are more flexible and offer the ability to
have multiple devices on the bus. In both of these cases, the
register control uses an I²C port.
STEREO (I²S/LEFT JUSTIFIED) OPERATING MODE
Stereo modes use both edges of FSYNC to determine placement
of data. Stereo mode is enabled when SAI_MODE = 0 and the
data format is determined by the SDATA_FMT register setting.
The I²S or left justified interface formats accept any number of
BCLK cycles per FSYNC cycle. Sample rates from 8 kHz to
192 kHz are accepted. The maximum BCLK rate is 24.576 MHz.
TDM OPERATING MODE
The TDM operating mode allows multiple chips to use a single
serial interface bus for audio data.
The FSYNC signal operates at the desired sample rate. A rising
edge of the FSYNC signal indicates the start of a new frame. For
proper operation, this signal must be one BCLK cycle wide,
transitioning on a falling BCLK edge. The MSB of data must be
present on the SDATA one BCLK cycle later. The SDATA signal
latches on the rising edge of BCLK.
Each chip on the TDM bus can occupy 16, 24, 32, 48, or 64 BCLK
cycles. This is set with the TDM_BCLKS bits and all devices on
the bus must have the same setting. Up to 16 SSM3515 devices can
be used on a single TDM bus, but only 4 unique I²C device
addresses are available. The SSM3515 automatically determines
how many possible devices can be placed on the bus from the
BCLK rate. There is no limit to the total number of BCLK cycles
per FSYNC pulse.
Which chip slot each SSM3515 uses is determined by the ADDR
pin settings (see Table 11 for details), or by the TDM_SLOT bits
in Register 0x05.
The input data width to the DAC can be either 16-bit or 24-bit.
SSM3515
I²C CONTROL
The SSM3515 supports a 2-wire serial (I²C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the SSM3515 and the system I²C master controller. The
SSM3515 is always a slave on the bus, meaning it cannot initiate
a data transfer. Each slave device is recognized by a unique address.
Using the ADDR pin provides the four device addresses, which are
listed in Table 11. The address byte format is shown in Table 13.
The address resides in the first seven bits of the I²C write. The
LSB of this byte sets either a read or write operation. Logic Level 1
corresponds to a read operation, and Logic Level 0 corresponds
to a write operation.
Connect 2.2 kΩ pull-up resistors on the lines connected to the
SDA and SCL pins. The voltage on these signal lines must not
be more than 5 V.
Addressing
Initially, each device on the I²C bus is in an idle state, monitoring
the SDA and SCL lines for a start condition and the proper
address. The I²C master initiates a data transfer by establishing a
start condition, defined by a high to low transition on SDA while
SCL remains high. This indicates that an address or data stream
follows. All devices on the bus respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/W bit)
MSB first. The device that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This ninth bit is an acknowledge bit. All other devices
withdraw from the bus at this point and return to the idle con-
dition. The device address for the SSM3515 is determined by the
state of the ADDR pin. See Table 11 for four available addresses.
The R/W bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means the master writes information to
the peripheral, whereas a Logic 1 means the master reads
information from the peripheral after writing the subaddress
and repeating the start address. A data transfer occurs until a
stop condition is encountered. A stop condition occurs when
SDA transitions from low to high while SCL is held high. The
timing for the I²C port is shown in Figure 61.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the SSM3515 immediately
jumps to the idle condition. During a given SCL high period,
the user must issue only one start condition, one stop condition, or
a single stop condition followed by a single start condition. If
the user issues an invalid subaddress, the SSM3515 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while in auto-increment mode,
one of two actions is taken.
Rev. 0| Page 21 of 41