ADV7160 Datasheet, PDF (21/44 Pages) Analog Devices – 96-Bit, 220 MHz True-Color Video RAM-DAC

ADV7160/ADV7162
R7
R9
R6
R6
R8
R5
R5
R7
R4
R4
R6
R3
R3
R5
R2
R2
G9
R1
R1
G8
R0
R0
G7
G7
G7
x
G7
G6
G6
G6
G5
G5
G5
G4
B9
G4
G3
B8
G3
G2
B7
G2
G1
B6
G1
B5
G0
G0
B7
x
x
B6
x
x
B5
x
x
x
B4
x
B3
x
x
B2
x
x
x
B1
x
x
B0
x
PIXEL
INPUT
DATA
PIN
DATA
ASSIGN- LATCHED
MENTS
TO
PIXEL PORT
R9
R8
R7
R6
R5
0
IOR
0
RED
0 _DAC
0
G9
G8
G7
G6
G5
G4
IOG
0
0 ^GREEN
DAC
0
0
B9
B8
B7
B6
B5
IOB
0
0 BLUE
0 ^DAC
0
0
DATA LATCHED
TO DAC INPUTS
Figure 29. 16-Bit True-Color in Bypass Mode using R7–R0
and G7–G0
R7
x
x
R9
R6
R6
R5
R8
R5
R4
R7
R4
R3
R6
R3
R2
R5
R2
R1
G9
R1
R0
G8
R0
G7
G7
G7
G6
G6
G6
G5
G5
G5
G4
B9
G4
G3
B8
G3
G2
B7
G2
G1
B6
G1
B5
G0
G0
x
B7
x
B6
x
x
B5
x
x
B4
x
x
B3
x
x
x
B2
x
x
B1
x
x
B0
x
PIXEL
INPUT
DATA
PIN
DATA
ASSIGN- LATCHED
MENTS
TO
PIXEL PORT
R9
R8
R7
R6
R5
0
IOR
0
RED
0 _DAC
0
G9
G8
G7
G6
G5
0
IOG
0
0 ^GREEN
DAC
0
0
B9
B8
B7
B6
B5
IOB
0
0 BLUE
0 ^DAC
0
0
DATA LATCHED
TO DAC INPUTS
Fiigure 30. 15-Bit True-Color in Bypass Mode using R6–R0
and G7–G0
In 15-bit Palette Bypass Mode, the color channels bypass the
Pixel Mask and the Color Palette. The 7 bits of red pixel data
and 8 bits of green pixel data are mapped onto the 5 MSBs of
the red, green and blue DAC input as shown in Figure 30. The
remaining LSBs on each DAC are zeros. The Bypass Mode can
be selected in two ways, by using CR27–CR24 of Command
Register 2 or on a pixel by pixel basis using the PS inputs
(ADV7160 only).
Multiplexing
The on-board multiplexers of the ADV7160/ADV7162 elimi-
nate the need for external data serializer circuits. Multiple video
memory devices can be connected, in parallel, directly to the de-
vice. Figure 31 shows four memory banks of 50 MHz memory
connected to the ADV7160, running in 4:1 multiplex mode,
giving a resultant pixel or dot clock rate of 200 MHz. Instead of
having to provide a new pixel at the input every 5 ns, four pixels
are provided together every 20 ns. The input multiplexer takes
the four pixels latched in parallel, and selects them one at a time
to produce a pixel stream at the pixel clock rate. In 4:1 mode,
the pixels are selected in the sequence A, B, C, D, cycling continu-
ously. In 2:1 mode, the A and B pixels are selected. The 8:1
mode is only available in 8-bit Pseudo-Color Mode. BLANK,
SYNC, ODD/EVEN and TRISYNC are not multiplexed and
can only change on a 1, 2, 4 or 8 pixel boundary depending on
the multiplex mode.
On the rising edge of LOADIN, all the pixel port inputs are
latched into the ADV7160/ADV7162. The LOADIN frequency
must be a divided down frequency of the pixel clock frequency.
This can be achieved using LOADOUT to directly drive
LOADIN as LOADOUT provides the correct frequency re-
quired, or drive LOADIN after delay through some external cir-
cuitry.
VIDEO MEMORY/
FRAME BUFFER
24
VRAM (BANK A) _{55050M0MMHHzHzz}
24
VRAM (BANK B) _{55050M0MMHHzHzz}
24
VRAM (BANK C) _{55050M0MMHHzHzz}
24
VRAM (BANK D) _{55050M0MMHHzHzz}
ADV7160/ADV7162
24
MULTIPLEXER
200MHz
(4 × 50MHz)
Figure 31. Direct Interfacing of Video Memory to
ADV7160/ADV7162
8-Bit Pseudo Color in 8:1 Multiplexing Mode
When 8:1 Multiplexing Mode is selected by setting Bit CR37 of
Command Register 3 to Logic “1” and bit CR36 of Command
Register 3 to Logic “0,” the ADV7160/ADV7162 goes into 8-
Bit Pseudo-Color Mode irrespective of the Color Mode selected
by Bits CR27 to CR24 in Command Register 2. Hence
LOADOUT operates at f_CLOCK/8. Eight 8-bit pixels are latched
in parallel by the rising edge of LOADIN. These 8-bit pixels
are then selected, one at a time, to produce an 8-bit pixel stream
which passes through the Pixel Mask to address the LUT. The
order the eight 8-bit pixels are displayed is GA, RA, GB, RB,
GC, RC, GD, RD.
REV. 0
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