ADSP-TS203S Datasheet, PDF (21/40 Pages) Analog Devices – TigerSHARC Embedded Processor

Preliminary Technical Data
ADSP-TS203S
ADSP-TS203S—SPECIFICATIONS
Note that component specifications are subject to change with-
out notice. For information on Link port electrical
characteristics, see Link Port Low-Voltage, Differential-Signal
(LVDS) Electrical Characteristics and Timing on page 27.
RECOMMENDED OPERATING CONDITIONS
Parameter
Test Conditions
Min Typ Max Unit
V_DD
V_{DD_A}
V_{DD_IO}
V_{DD_DRAM}
T_CASE
V_IH
V_IL
I_DD
I_{DD_A}
I_{DD_IO}
Internal Supply Voltage
0.95
1.05 V
Analog Supply Voltage
0.95
1.05 V
I/O Supply Voltage
2.38
2.63 V
Internal DRAM Supply Voltage
1.425
1.575 V
Case Operating Temperature
–40
+85 °C
High-Level Input Voltage¹
Low-Level Input Voltage¹
V_DD supply current for typical activity²
@ V_DD, V_{DD_IO} = max
@ V_DD, V_{DD_IO} = min
@ CCLK=500 MHz, V_DD=1.0 V, T_CASE=25ºC
1.7
3.63 V
–0.5
0.8 V
2.39
A
V_{DD_A} supply current for typical activity
@ CCLK=500 MHz, V_DD=1.0 V, T_CASE=25ºC
V_{DD_IO} supply current for typical activity² (DRAM @ SCLK=100 MHz, V_{DD_IO}=2.5 V, T_CASE=25ºC,
Internal Regulator Disabled)
ENEDREG=0
20 50 mA
0.16
A
I_{DD_DRAM}
V_{DD_DRAM} supply current for typical activity^2,3
V_REF
SCLK_V_REF
Voltage reference
Voltage reference
@ CCLK=500 MHz, V_{DD_DRAM}=1.5 V,
T_CASE=25ºC, ENEDREG=0
0.40
A
(V_{DD_IO} × 0.56)⁴
V
(V_{DD_IO} × 0.56)⁴
V
1 _{Applies to input and bidirectional pins.}
2 _{For details on internal and external power calculation issues, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices website.}
3 _{For ENEDREG=1, the internal DRAM supply is used; there is no IDD_DRAM for this condition.}
4 _{If the clock driver voltage is > 2.8 V and the clock driver voltage is used to generate SCLK_VREF, this formula becomes: (VCLOCK_DRIVE/2) ±5%)}
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Max Unit
V_OH
High-Level Output Voltage¹
V_OL
Low-Level Output Voltage¹
@V_{DD_IO} = min, I_OH = –2 mA
@V_{DD_IO} = min, I_OL = 4 mA
2.18
V
0.4 V
I_IH
High-Level Input Current
@V_{DD_IO} = max, V_IN = V_{DD_IO} max
10 µA
I_{IH_PU}
High-Level Input Current
@V_{DD_IO} = max, V_IN = V_{DD_IO} max
50 µA
I_{IH_PD}
High-Level Input Current
@V_{DD_IO} = max, V_IN = V_{DD_IO} max
0.3
0.76 mA
I_IL
Low-Level Input Current
@V_{DD_IO} = max, V_IN = 0V
10 µA
I_{IL_PU}
Low-Level Input Current
@V_{DD_IO} = max, V_IN = 0V
0.3
0.76 mA
I_{IL_PU_AD}
Low-Level Input Current
@V_{DD_IO} = max, V_IN = 0V
0.03
0.1 mA
I_OZH
Three-State Leakage Current High
@V_{DD_IO} = max, V_IN = V_{DD_IO} max
10 µA
I_{OZH_PD}
Three-State Leakage Current High
@V_{DD_IO} = max, V_IN = V_{DD_IO} max
0.3
0.76 mA
I_OZL
Three-State Leakage Current Low
@V_{DD_IO} = max, V_IN = 0V
10 µA
I_{OZL_PU}
Three-State Leakage Current Low
@V_{DD_IO} = max, V_IN = 0
0.3
0.76 mA
I_{OZL_PU_AD} Three-State Leakage Current Low
@V_{DD_IO} = max, V_IN = 0
0.03
0.1 mA
I_{OZL_OD}
C_IN
Three-State Leakage Current Low
Input Capacitance^2,3
@V_{DD_IO} = max, V_IN = 0V
@f_IN = 1MHz,T_CASE = 25C, V_IN = 2.5V
4
7.6 mA
3
pF
Parameter name suffix conventions: no suffix = applies to pins without pullup or pull down resistors, _PD = applies to pin types (pd) or
(pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD
1 _{Applies to output and bidirectional pins.}
2 _{Applies to all signals.}
3 _{Guaranteed but not tested.}
Rev. PrB | Page 21 of 40 | December 2003