ADSP-21160M_15 Datasheet, PDF (21/60 Pages) Analog Devices – SHARC Digital Signal Processor

ADSP-21160M/ADSP-21160N
Table 12. Power-Up Sequencing
Parameter
Min
Max
Unit
Timing Requirements
t_RSTVDD
RESET Low Before V_DDINT/V_DDEXT on
t_IVDDEVDD
V_DDINT on Before V_DDEXT
t_CLKVDD
CLKIN Running After valid V_DDINT/V_DDEXT1
t_CLKRST
CLKIN Valid Before RESET Deasserted
t_PLLRST
PLL Control Setup Before RESET Deasserted
Switching Characteristics
t_CORERST
DSP Core Reset Deasserted After RESET Deasserted
0
– 50
0
10²
20³
4096t_CK3, ⁴
ns
+ 200
ms
200
ms
μs
μs
1 _{Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their VDDINT and VDDEXT rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,}
depending on the design of the power supply subsystem.
2 _{Assumes a stable CLKIN signal after meeting worst-case start-up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start-up time.}
3 _{Based on CLKIN cycles.}
4 _{CORERST is an internal signal only. The 4096 cycle count is dependent on tSRST specification. If setup time is not met, one additional CLKIN cycle may be added to the core}
reset time, resulting in 4097 cycles maximum.
RESET
V_DDINT
V_DDEXT
CLKIN
t_RSTVDD
t_IVDDEVDD
t_CLKVDD
t_CLKRST
CLK_CFG3-0
CORERST
t_PLLRST
t_CORERST
Figure 8. Power-Up Sequencing
Rev. C | Page 21 of 60 | February 2013