ADF7020_15 Datasheet, PDF (21/48 Pages) Analog Devices – High Performance, ISM Band, FSK/ASK Transceiver IC

Data Sheet
RSSI/AGC
The RSSI is implemented as a successive compression log amp
following the baseband channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. The RSSI itself
is used for amplitude shift keying (ASK) demodulation. In ASK
mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integra-
tor in feedback around the log amp. This uses the baseband
offset clock divide. The RSSI level is converted for user
readback and digitally controlled AGC by an 80-level (7-bit)
flash ADC. This level can be converted to input power in dBm.
OFFSET
CORRECTION
1
A
A
A
LATCH
FSK
DEMOD
FWR FWR FWR FWR
CLK
R
ADC
RSSI
ASK
DEMOD
NOTES
1. FWR = FULL WAVE RECTIFIER
Figure 29. RSSI Block Diagram
RSSI Thresholds
When the RSSI is above AGC_HIGH_THRESHOLD, the gain
is reduced. When the RSSI is below AGC_LOW_THRESHOLD,
the gain is increased. A delay (AGC_DELAY) is programmed
to allow for settling of the loop. The user programs the two
threshold values (recommended defaults of 30 and 70) and the
delay (default of 10). The default AGC setup values should be
adequate for most applications. The threshold values must be
chosen to be more than 30 apart for the AGC to operate
correctly.
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits
R3_DB[4:5] to give an offset clock between 1 MHz and 2 MHz.
BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE)
where BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
AGC Information and Timing
AGC is selected by default, and operates by selecting the appropri-
ate LNA and filter gain settings for the measured RSSI level. It
is possible to disable AGC by writing to Register 9 if entering
one of the modes listed in Table 5 is desired, for example. The
time for the AGC circuit to settle and, therefore, the time to
take an accurate RSSI measurement is typically 150 µs, although
this depends on how many gain settings the AGC circuit has to
cycle through. After each gain change, the AGC loop waits for
a programmed time to allow transients to settle.
ADF7020
This wait time can be adjusted to speed up this settling by
adjusting the appropriate parameters.
AGC _Wait _Time =
AGC _ DELAY × SEQ _CLK
XTAL
AGC Settling = AGC_Wait_Time × Number of Gain Changes
Thus, in the worst case, if the AGC loop has to go through all
5 gain changes, AGC_Delay =10, SEQ_CLK = 200 kHz, AGC
Settling = 10 × 5 µs × 5 = 250 µs. Minimum AGC_Wait_Time
needs to be at least 25 µs.
RSSI Formula (Converting to dBm)
Input_Power [dBm] = −120 dBm + (Readback_Code +
Gain_Mode_Correction) × 0.5
where:
Readback_Code is given by Bit RV7 to Bit RV1 in the readback
register (see the Readback Format section).
Gain_Mode_Correction is given by the values in Table 6.
LNA gain and filter gain (LG2/LG1, FG2/FG1) are also
obtained from the readback register.
Table 6. Gain Mode Correction
LNA Gain
(LG2, LG1)
Filter Gain
(FG2, FG1)
H (1,1)
H (1,0)
M (1,0)
H (1,0)
M (1,0)
M (0,1)
M (1,0)
L (0,0)
L (0,1)
L (0,0)
EL (0,0)
L (0,0)
Gain Mode Correction
0
24
45
63
90
105
An additional factor should be introduced to account for losses
in the front-end matching network/antenna.
FSK DEMODULATORS ON THE ADF7020
The two FSK demodulators on the ADF7020 are
• FSK correlator/demodulator
• Linear demodulator
Select these using the demodulator select bits, R4_DB[4:5].
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform band-
pass filtering of the binary FSK frequencies at (IF + f_DEV) and
(IF − f_DEV). Data is recovered by comparing the output levels
from each of the two correlators. The performance of this fre-
quency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in
the presence of additive white Gaussian noise (AWGN).
Rev. D | Page 21 of 48