AD9913 Datasheet, PDF (21/32 Pages) Analog Devices – Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer

POWER-DOWN FEATURES
The AD9913 supports an externally controlled power-down
feature as well as software programmable power-down bits
consistent with other Analog Devices, Inc. DDS products.
The external PWR_DWN_CTL pin determines the power-
down scheme. A low on this pin allows the user to power down
DAC, PLL, input clock circuitry, and the digital section of the
chip individually via the unique control bits, CFR1 [6:4]. In this
mode, CFR1 [7] is inactive.
When the PWR_DWN_CTL is set, CFR1 [6:4] lose their
meaning. At the same time, the AD9913 provides two different
power-down modes based on the value of CFR1 [7]: a fast
recovery power-down mode in which only the digital logic and
the DAC digital logic are powered down, and a full power-down
mode in which all functions are powered down. A significant
amount of time is required to recover from power-down mode.
Table 11 indicates the logic level for each power-down bit that
drives out of the AD9913 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
AD9913
Table 8. Power-Down Controls
Control
Mode Active
PWR_DWN_CTL = 0 Software
CFR1 [7] = don’t
Control
care
PWRDWNCTL = 1
CFR1 [7] = 0
PWRDWNCTL = 1
CFR1 [7] = 1
External
Control,
Fast recovery
power-down
mode
External
Control,
Full power-
down mode
Description
Digital power-down = CFR1 [6]
DAC power-down = CFR1 [5]
Input clock power-down =
CFR1 [4]
N/A
N/A
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