AD9225_03 Datasheet, PDF (21/24 Pages) Analog Devices – Complete 12-Bit, 25 MSPS Monolithic A/D Converter

AD9225
The digital activity on the AD9225 chip falls into two general
categories: correction logic and output drivers. The internal
correction logic draws relatively small surges of current, mainly
during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits; large capacitive loads are to be avoided. Note that
the internal correction logic of the AD9225 is referenced to
AVDD while the output drivers are referenced to DRVDD.
The decoupling shown in Figure 34, a 0.1 mF ceramic chip
capacitor and a 10 mF tantalum capacitor, are appropriate for a
reasonable capacitive load on the digital outputs (typically
20 pF on each pin). Applications involving greater digital loads
should consider increasing the digital decoupling proportionally,
and/or using external buffers/latches.
10␮F 0.1␮F
DRVDD
AD9225
DRVSS
Figure 34. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low frequency
ripple to negligible levels. Refer to the AD9225/AD9225EB
schematic and layouts in Figures 35 to 41 for more information
regarding the placement of decoupling capacitors.
REV. B
–21–