AD8196_15 Datasheet, PDF (21/24 Pages) Analog Devices – 2:1 HDMI/DVI Switch with Equalization

AD8196
TMDS Terminations
The AD8196 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
The output termination resistors of the AD8196 back-terminate
the output TMDS transmission lines. These back-terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8196
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
These four signals can be switched through the auxiliary bus of
the AD8196 and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8196 is being used.
For example, the maximum speed of signals present on the
auxiliary lines are 100 kHz I²C data on the DDC lines, therefore,
any layout that enables 100 kHz I²C to be passed over the DDC
bus should suffice. The HDMI 1.3 specification, however, places
a strict 50 pF limit on the amount of capacitance that can be
measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8196, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stackup, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
the amount of parasitic trace capacitance. An example of the
board stackup is shown in Figure 33.
3W
W
3W
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
Figure 33. Example Board Stackup
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement of
this signal is not critical, but it should be routed as directly as
possible.
When the AD8196 is powered up, one set of the auxiliary inputs
is passively routed to the outputs. In this state, the AD8196 looks
like a 100 Ω resistor between the selected auxiliary inputs and
the corresponding outputs as illustrated in Figure 27. The AD8196
does not buffer the auxiliary signals, therefore, the input traces,
output traces, and the connection through the AD8196 all must
be considered when designing a PCB to meet HDMI/DVI speci-
fications. The unselected auxiliary inputs of the AD8196 are placed
into a high impedance mode when the device is powered up. To
ensure that all of the auxiliary inputs of the AD8196 are in a high
impedance mode when the device is powered off, it is necessary to
power the AMUXVCC supply as illustrated in Figure 28.
In contrast to the auxiliary signals, the AD8196 buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.
Power Supplies
The AD8196 has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are
• AVCC/AVEE
• VTTI/AVEE
• VTTO/AVEE
• DVCC/DVEE
• AMUXVCC/DVEE
The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies
power the core of the AD8196. The VTTI/AVEE supply (3.3 V)
powers the input termination (see Figure 25). Similarly, the
VTTO/AVEE supply (3.3 V) powers the output termination
(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)
powers the auxiliary multiplexer core and determines the
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