AD7986BCPZ Datasheet, PDF (21/28 Pages) Analog Devices – 18-Bit, 2 MSPS PulSAR 15 mW ADC in LFCSP (QFN)

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7986 devices are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7986 devices is
shown in Figure 29, and the corresponding timing is given in
Figure 30.
With SDI high, a rising edge on CNV initiates a conversion, selects
the CS mode, and forces SDO to high impedance. In this mode,
CNV must be held high during the conversion phase and the
subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
AD7986
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7986 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 18^th SCK falling edge, SDO returns to high impedance and
another AD7986 can be read.
CNV
SDI AD7986 SDO
CNV
SDI AD7986 SDO
CS2
CS1
CONVERT
DIGITAL HOST
SCK
SCK
DATA IN
CLK
Figure 29. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
t_CONV
t_DATA
t_CYC
t_CONV
t_DATA
CNV
ACQUISITION
(n – 1)
SDI
SCK
SDO
CONVERSION (n – 1)
t_HSDICNV
(I/O QUIET
TIME)
t_ACQ
ACQUISITION (n)
(QUIET
TIME)
CONVERSION (n)
t_SSDICNV
16 17 18
t_EN
t_EN
12
t_HSDO
t_DSDO
t_QUIET
16 17 18
t_SCK
21
0
17 16 15
210
END DATA (n – 2)
t_HSDO
BEGIN DATA (n – 1)
t_{DIS END DATA (n – 1)}
Figure 30. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
(I/O QUIET ACQUISITION
TIME)
(n + 1)
t_DIS
Rev. B | Page 21 of 28