AD7686_15 Datasheet, PDF (21/28 Pages) Analog Devices – 16-Bit, 500 kSPS PulSAR

Data Sheet
CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7686s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7686s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback.
AD7686
When the conversion is complete, the MSB is output onto SDO,
and the AD7686 enters the acquisition phase and powers down.
The remaining data bits stored in the internal shift register are
then clocked by subsequent SCK falling edges. For each ADC,
SDI feeds the input of the internal shift register and is clocked
by the SCK falling edge. Each ADC in the chain outputs its data
MSB first, and 16 × N clocks are required to read back the N
ADCs. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate and, consequently,
more AD7686s in the chain, provided the digital host has an
acceptable hold time. The maximum conversion rate can be
reduced due to the total readback time. For instance, with a 3 ns
digital host setup time and 3 V interface, up to four AD7686s
running at a conversion rate of 360 kSPS can be daisy-chained
on a 3-wire port.
CONVERT
CNV
SDI AD7686 SDO
A
SCK
CNV
SDI AD7686 SDO
B
SCK
DIGITAL HOST
DATA IN
CLK
Figure 41. Chain Mode, No Busy Indicator Connection Diagram
SDI_A = 0
CNV
ACQUISITION
SCK
t_HSCKCNV
SDO_A = SDI_B
SDO_B
t_CYC
t_CONV
CONVERSION
t_SSCKCNV
t_EN
t_ACQ
ACQUISITION
t_SCKL
t_SCK
1
2
3
t_SSDISCK
D_A15
t_HSDO
t_DSDO
D_B15
D_A14
D_B14
D_A13
D_B13
14
15
16
17
18
t_HSDISCK
t_SCKH
D_A1
D_A0
D_B1 D_B0 D_A15 D_A14
Figure 42. Chain Mode, No Busy Indicator Serial Interface Timing
30
31
32
D_A1
D_A0
Rev. C | Page 21 of 28