ADSP21062 Datasheet, PDF (20/48 Pages) Analog Devices – DSP Microcomputer Family

ADSP-21062/ADSP-21062L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
Parameter
Min
Timing Requirements:
t_DAD
t_DRLD
t_HDA
t_HDRH
t_DAAK
t_DSAK
Address, Selects Delay to Data Valid^{1, 4}
RD Low to Data Valid¹
Data Hold from Address, Selects²
0.5
Data Hold from RD High²
2.0
ACK Delay from Address, Selects^{3, 4}
ACK Delay from RD Low³
ADSP-21062
Max
ADSP-21062L
Min
Max
Units
18 + DT + W
12 + 5DT/8 + W
0.5
2.0
14 + 7DT/8 + W
8 + DT/2 + W
18 + DT + W ns
12 + 5DT/8 + W ns
ns
ns
14 + 7DT/8 + W ns
8 + DT/2 + W ns
Switching Characteristics:
t_DRHA
t_DARL
t_RW
t_RWR
Address, Selects Hold After RD High
Address, Selects to RD Low⁴
RD Pulsewidth
RD High to WR, RD, DMAGx Low
t_SADADC Address, Selects Setup Before
ADRCLK High⁴
0+H
2 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
0 + DT/4
0+H
ns
2 + 3DT/8
ns
12.5 + 5DT/8 + W
ns
8 + 3DT/8 + HI
ns
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × t_CK.
HI = t_CK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t_CK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1_{Data Delay/Setup: User must meet t DAD or tDRLD or synchronous spec tSSDATI.}
2_{Data Hold: User must meet tHDA or tHDRH or synchronous spec tHSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times}
given capacitive and dc loads.
3_{ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-}
tion of ACK (High).
4_{The falling edge of MSx, SW, BMS is referenced.}
ADDRESS
MSx, SW
BMS
RD
DATA
ACK
t_DARL
t_RW
t_DAAK
t_DAD
t_DRLD
t_DSAK
t_DRHA
t_HDA
t_HDRH
t_RWR
WR, DMAG
ADRCLK
(OUT)
t_SADADC
Figure 13. Memory Read—Bus Master
–20–
REV. B