AD7993_15 Datasheet, PDF (20/32 Pages) Analog Devices – 4-Channel, 10- and 12-Bit ADCs with IC Compatible Interface in 16-Lead TSSOP

AD7993/AD7994
CONVERSION RESULT REGISTER
The conversion result register is a 16-bit read-only register that
stores the conversion result from the ADC in straight binary
format. A 2-byte read is necessary to read data from this
register. Table 13 shows the contents of the first byte to be read
from the AD7993/AD7994 and Table 14 shows the contents of
the second byte to be read.
Table 13. Conversion Value Register (First Read)
D15
D14 D13 D12 D11 D10 D9 D8
Alert_Flag Zero CHID1 CHID0 MSB B10 B9 B8
Table 14. Conversion Value Register (Second Read)
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1/0 B0/0
The conversion result of the AD7993/AD7994 consists of an
Alert_Flag bit, a zero bit, two channel identifier bits, and the
10- and 12-bit data result. For the AD7993, the 2 LSB (D1 and
D0) of the second read contain two trailing 0s.
The Alert_Flag bit indicates whether the conversion result
being read or any other channel result has violated the limit
registers associated with it. If an alert occurs, the master may
wish to read the alert status register to obtain more information
on where the alert occurred if the Alert_Flag bit is set.
The Alert_Flag bit is followed by a zero bit and two channel
identifier bits that indicate which channel the conversion result
corresponds to. These, in turn, are followed by the 10- bit and
12-bit conversion result, MSB first.
Table 15. Channel Identifier Bits
Alert_Flag Zero CHID1 CHID0
0/1
0
0
0
0/1
0
0
1
0/1
0
1
0
0/1
0
1
1
Channel No. Result
Channel 1 (VIN1)
Channel 2 (VIN2)
Channel 3 (VIN3)
Channel 4 (VIN4)
LIMIT REGISTERS
The AD7993/AD7994 have four pairs of limit registers. Each
pair stores high and low conversion limits for each analog
input channel. Each pair of limit registers has one associated
hysteresis register. All 12 registers are 16 bits wide; only the
12 LSBs of the registers are used for the AD7993/AD7994. For
the AD7993, the 2 LSBs, D1 and D0, should contain 0s. On
power-up, the contents of the DATAHIGH register for each
channel is full scale, while the contents of the DATALOW
registers is zero scale by default. The AD7993/AD7994 signal
an alert (in either hardware, software, or both, depending on
configuration) if the conversion result moves outside the upper
or lower limit set by the limit registers.
DATA_HIGH Register CH1/CH2/CH3/CH4
The DATAHIGH registers for each channel are 16-bit read/write
registers; only the 12 LSBs of each register are used. This
register stores the upper limit that activates the alert output
and/or the Alert_Flag bit in the conversion result register. If the
value in the conversion result register for a channel is greater
than the value in the DATAHIGH register for that channel, an
alert occurs. When the conversion result returns to a value at
least N LSB below the DATAHIGH register value, the ALERT
output pin and Alert_Flag bit are reset. The value of N is taken
from the hysteresis register associated with that channel. The
ALERT pin can also be reset by writing to Bits D2 and D1 in the
configuration register. For the AD7993, D1 and D0 of the
DATAHIGH register should contain 0s.
Table 16. DATAHIGH Register (First Read/Write)
D15 D14 D13 D12 D11 D10 D9 D8
0
0
0
0
B11 B10 B9 B8
Table 17. DATAHIGH Register (Second Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
DATA_LOW Register CH1/CH2/CH3/CH4
The DATALOW register for each channel is a 16-bit read/write
register; only the 12 LSBs of each register are used. The register
stores the lower limit that activates the ALERT output and/or
the Alert_Flag bit in the conversion result register. If the value
in the conversion result register for a channel is less than the
value in the DATALOW register for that channel, an ALERT
occurs. When the conversion result returns to a value at least N
LSB above the DATALOW register value, the ALERT output pin
and Alert_Flag bit are reset. The value of N is taken from the
hysteresis register associated with that channel. The ALERT
output pin can also be reset by writing to Bits D2 and D1 in the
configuration register. For the AD7993, D1 to D0 of the
DATALOW register should contain 0s.
Table 18. DATALOW Register (First Read/Write)
D15 D14 D13 D12 D11 D10 D9 D8
0
0
0
0
B11 B10 B9 B8
Table 19. DATALOW Register (Second Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
B7 B6 B5 B4 B3 B2 B1 B0
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