AD7685_15 Datasheet, PDF (20/28 Pages) Analog Devices – 16-Bit, 250 kSPS PulSAR

AD7685
CS MODE 4-WIRE, NO BUSY INDICATOR
This mode is usually used when multiple AD7685s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7685s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
Data Sheet
conversion is complete, the AD7685 enters the acquisition phase
and powers down. Each ADC result can be read by bringing low
its SDI input, which consequently outputs the MSB onto SDO.
The remaining data bits are then clocked by subsequent SCK
falling edges. The data is valid on both SCK edges. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge will allow a faster reading rate, provided it
has an acceptable hold time. After the 16th SCK falling edge, or
when SDI goes high, whichever is earlier, SDO returns to high
impedance and another AD7685 can be read.
If multiple AD7685s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CS2
CS1
CONVERT
CNV
SDI AD7685 SDO
CNV
SDI AD7685 SDO
DIGITAL HOST
SCK
SCK
DATA IN
CLK
Figure 38. CS Mode 4-Wire, No BUSY Indicator Connection Diagram
CNV
ACQUISITION
t_CONV
CONVERSION
t_SSDICNV
SDI(CS1)
t_HSDICNV
t_CYC
t_ACQ
ACQUISITION
SDI(CS2)
SCK
SDO
t_SCKL
t_SCK
1
2
3
14
15
16
t_HSDO
t_EN
t_SCKH
t_DSDO
D15 D14 D13
D1 D0
17
18
D15 D14
30
31
32
t_DIS
D1 D0
Figure 39. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev. D | Page 20 of 28