AD7142 Datasheet, PDF (20/68 Pages) Analog Devices – Programmable Capacitance-to-Digital Converter with Environmental Compensation

AD7142
FIFO CONTROL
As shown in Figure 30, there are a number of FIFOs
implemented on the AD7142. These FIFOs are located in
Bank 3 of the on-chip memory. The FIFOs are used by the on-
chip logic to run the environmental calibration, adaptive
threshold, and proximity algorithms.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12]are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP. These values determine which CDC samples
are not used (skipped) in the slow FIFO. Changing theses values
slows down or speeds up the rate at which the ambient
capacitance value tracks the measured capacitance value read by
the converter.
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples
from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many
conversion stages are in a sequence.
Table 13. FF_SKIP_CNT Settings
FF_SKIP_CNT FAST FIFO Update Rate
DECIMATION = 128
0
1.536 × (SEQUENCE_STAGE_NUM + 1) ms
1
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
2
4.608 × (SEQUENCE_STAGE_NUM + 1) ms
3
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
4
7.68 × (SEQUENCE_STAGE_NUM + 1) ms
5
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
6
10.752 × (SEQUENCE_STAGE_NUM + 1) ms
7
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
8
13.824 × (SEQUENCE_STAGE_NUM + 1) ms
9
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
10
16.896 × (SEQUENCE_STAGE_NUM + 1) ms
11
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
12
19.968 × (SEQUENCE_STAGE_NUM + 1) ms
13
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
14
23.04 × (SEQUENCE_STAGE_NUM + 1) ms
15
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
Determining the AVG_FP_SKIP and AVG_LP_SKIP value is
only required once during the initial setup of the capacitance
sensor interface. Recommended values for these settings when
using all 12 conversion stages on the AD7142 are:
AVG_FP_SKIP = 11 = skip 31 samples
AVG_LP_SKIP = 11 = skip 3 samples
FF_SKIP_CNT
In Register 0x02, Bits[3:0] are the fast filter skip control,
FF_SKIP_CNT. This value determines which CDC samples are
not used (skipped) in the proximity detection fast FIFO.
The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected . The fast FIFO expects to
receive samples from the converter at a set rate. FF_SKIP_CNT
is used to normalize the frequency of the samples going into the
FIFO, regardless of how many conversion stages are in a
sequence.
Determining the FF_SKIP_CNT value is required only once
during the initial setup of the capacitance sensor interface.
Table 13 shows how FF_SKIP_CNT controls the update rate to
the fast FIFO. Recommended value for this setting when using
all 12 conversion stages on the AD7142 is:
FF_SKIP_CNT = 0000 = no samples skipped
DECIMATION = 256
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
27.648 × (SEQUENCE_STAGE_NUM + 1) ms
30.72 × (SEQUENCE_STAGE_NUM + 1) ms
33.792 × (SEQUENCE_STAGE_NUM + 1) ms
36.864 × (SEQUENCE_STAGE_NUM + 1) ms
39.936 × (SEQUENCE_STAGE_NUM + 1) ms
43.008 × (SEQUENCE_STAGE_NUM + 1) ms
46.08 × (SEQUENCE_STAGE_NUM + 1) ms
49.152 × (SEQUENCE_STAGE_NUM + 1) ms
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