AD5684ARUZ-RL7 Datasheet, PDF (20/28 Pages) Analog Devices – Quad, 16-/12-Bit nanoDAC+ with SPI Interface

AD5686/AD5684
STANDALONE OPERATION
The write sequence begins by bringing the SYNC line low. Data
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is
clocked in, SYNC should be brought high. The programmed
function is then executed, that is, an LDAC-dependent change
in DAC register contents and/or a change in the mode of
operation. If SYNC is taken high at a clock before the 24^th
clock, it is considered a valid frame and invalid data may be
loaded to the DAC. SYNC must be brought high for a minimum
of 20 ns (single channel, see t8 in Figure 2) before the next write
sequence so that a falling edge of SYNC can initiate the next
write sequence. SYNC should be idle at rails between write
sequences for even lower power operation of the part.
The SYNC line is kept low for 24 falling edges of SCLK, and the
DAC is updated on the rising edge of SYNC.
After data is transferred into the input register of the addressed
DAC, all DAC registers and outputs can be updated by
taking LDAC low while the SYNC line is high.
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on LDAC)
Command 0001 allows the user to write to each DAC’s
dedicated input register individually. When LDAC is low,
the input register is transparent (if not controlled by the
LDAC mask register).
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the
contents of the selected input registers and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent of
LDAC)
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This function
is enabled through a software executable daisy-chain enable
(DCEN) command. Command 1000 is reserved for this DCEN
function (see Table 8). The daisy-chain mode is enabled by
setting Bit DB0 in the DCEN register. The default setting is
standalone mode, where DB0 = 0. Table 10 shows how the state
of the bit corresponds to the mode of operation of the device.
Table 10. Daisy-Chain Enable (DCEN) Register
DB0
Description
0
Standalone mode (default)
1
DCEN mode
68HC11*
MOSI
SCK
PC7
PC6
MISO
Data Sheet
AD5686/
AD5684
SDIN
SCLK
SYNC
LDAC
SDO
SDIN
AD5686/
AD5684
SCLK
SYNC
LDAC
SDO
SDIN
AD5686/
AD5684
SCLK
SYNC
LDAC
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Daisy-Chaining the AD5686/AD5684
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting the SDO line to
the SDIN input on the next DAC in the chain, a daisy-chain
interface is constructed. Each DAC in the system requires 24
clock pulses. Therefore, the total number of clock cycles must
equal 24 × N, where N is the total number of devices that are
updated. If SYNC is taken high at a clock that is not a multiple
of 24, it is considered a valid frame and invalid data may be
loaded to the DAC. When the serial transfer to all devices is
complete, SYNC is taken high. This latches the input data in
each device in the daisy chain and prevents any further data
from being clocked into the input shift register. The serial clock
can be continuous or a gated clock. A continuous SCLK source
can be used only if SYNC can be held low for the correct
number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used,
and SYNC must be taken high after the final clock to latch the data.
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