OP15 Datasheet, PDF (2/12 Pages) Analog Devices – Precision JFET-Input Operational Amplifiers

OP15/OP17–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V_S = ؎15 V, T_A = 25^؇C, unless otherwise noted)
Parameter
Symbol Conditions
OP15A, OP15E
OP17A, OP17E
Min Typ Max
OP15F
OP17F
Min Typ Max
OP15G
OP17G
Min Typ Max Unit
Input Offset Voltage V_OS
Input Offset Current I_OS
OP15
OP17
R_S = 50 W
T_J = 25∞C¹
Device Operating
T_J = 25∞C¹
Device Operating
0.2 0.5
3
10
5
22
3
10
5
25
0.4 1.0
6
20
10 40
6
20
10 50
0.5 3.0 mV
12 50 pA
20 100 pA
12 50 pA
20 125 pA
Input Bias Current I_B
OP15
OP17
Input Resistance
R_IN
T_J = 25∞C¹
Device Operating
T_J = 25∞C¹
Device Operating
± 15 ± 50
± 18 ± 110
± 15 ± 50
± 20 ± 130
10¹²
± 30 ± 100
± 40 ± 200
± 30 ± 100
± 40 ± 250
10¹²
± 60 ± 200 pA
± 80 ± 400 pA
± 60 ± 200 pA
± 80 ± 500 pA
10¹²
W
Large-Signal
Voltage Gain
A_VO
R_L ≥ 2 kW
V_O = ± 10 V
100 240
75
220
50
200
V/mV
Output Voltage
V_O
Swing
Supply Current
I_SY
R_L = 10 kW
R_L = 2 kW
OP15
OP17
± 12 ± 13
± 11
± 12.7
± 12 ± 13
± 11 ± 12.7
2.7 4.0
4.6 7.0
2.7 4.0
4.6 7.0
± 12
± 13
V
± 11
± 12.7
V
2.8 5.0 mA
4.8 8.0 mA
Slew Rate²
Gain Bandwidth³
Product
SR
GBW
A_VCL = 1, OP15
A_VCL = 5, OP17
OP15
OP17
10
13
45
60
4.0
6.0
20
30
7.5
11
35
50
3.5
5.7
15
28
5
9
25
40
3.0
5.4
11
26
V/ms
V/ms
MHz
MHz
Closed-Loop
CLBW
A_VCL = 1, OP15
14
13
Bandwidth
A_VCL = 5, OP17
11
10
12
MHz
9
MHz
Settling Time
t_S
OP15
OP17
To 0.01%
To 0.05%
To 0.10%
To 0.01%
To 0.05%
To 0.10%
4.5
4.5
1.5
1.5
1.2
1.2
1.5
1.5
0.7
0.7
0.6
0.6
4.7
ms
1.6
ms
1.3
ms
1.6
ms
0.8
ms
0.7
ms
Input Voltage Range IVR
± 10.5
± 10.5
± 10.3
V
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Input Noise
Voltage Density
Input Noise
Current Density
CMRR
PSRR
e_n
i_n
V_CM = ± 10.5 V
V_CM = ± 10.3 V
V_S = ± 10 V to ± 18 V
V_S = ± 10 V to ± 18 V
f_O = 100 Hz
f_O = 1 kHz
f_O = 100 Hz
f_O = 1 kHz
86
100
86
100
dB
82
96
dB
10 51
20
15
0.01
0.01
10 51
20
15
0.01
0.01
10 80
20
15
0.01
0.01
mV/V
mV/V
nV/÷Hz
nV/÷Hz
pA/÷Hz
pA/÷Hz
Input Capacitance C_IN
3
3
3
pF
NOTES
1_{Input bias current is specified for two different conditions. The TJ = 25∞C specification is with the junction at ambient temperature; the device operating specification}
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of I_B versus T_J and I_B versus T_A. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I _B and
I_OS are measured at V_CM = 0.
2_{Settling time is defined here for a unity gain inverter connection using 2 kW resistors. It is the time required for the error voltage (the voltages at the inverting input pit}
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit.
3_{Sample tested.}
4_{Settling time is defined here for AV = –5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to}
settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit.
–2–
REV. A