MT-008 Datasheet, PDF (2/10 Pages) Analog Devices – Converting Oscillator Phase Noise to Time Jitter

MT-008
The sampling process is basically a multiplication of the sampling clock and the analog input
signal. This is multiplication in the time domain, which is equivalent to convolution in the
frequency domain. Therefore, the spectrum of the sampling clock oscillator is convolved with
the input and shows up on the FFT output of a pure sinewave input signal (see Figure 2).
ANALOG
INPUT, f_o
IDEAL
ADC
N→∞
DSP
SNR
f
f_o
IDEAL SINEWAVE
INPUT
f_s
CLOSE-IN
BROADBAND
f
f_s
SAMPLING CLOCK
WITH PHASE NOISE
f
f_o
FFT OUTPUT
SNR = 20log ₁₀
1
2π f_ot_j
(MEASURED FROM DC TO f_s/2)
FOR IDEAL ADC
WITH N → ∞
Figure 2: Effect of Sampling Clock Phase Noise Ideal Digitized Sinewave
The "close-in" phase noise will "smear" the fundamental signal into a number of frequency bins,
thereby reducing the overall spectral resolution. The "broadband" phase noise will cause a
degradation in the overall SNR as predicted by Eq. 1 (Reference 1 and 2):
SNR
=
20
log₁₀
⎡
⎢
⎢⎣
1
2πf t
j
⎤
⎥
⎥⎦
.
Eq. 1
It is customary to characterize an oscillator in terms of its single-sideband phase noise as shown
in Figure 3, where the phase noise in dBc/Hz is plotted as a function of frequency offset, f_m, with
the frequency axis on a log scale. Note the actual curve is approximated by a number of regions,
each having a slope of 1/f ^x, where x = 0 corresponds to the "white" phase noise region (slope = 0
dB/decade), and x = 1 corresponds to the "flicker" phase noise region (slope = –20 dB/decade).
There are also regions where x = 2, 3, 4, and these regions occur progressively closer to the
carrier frequency.
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