EVAL-AD421EB Datasheet, PDF (2/7 Pages) Analog Devices – Evaluation Board for Loop Powered 4-20mA DAC

EVAL-AD421EB
Link Options
There is one link option on the evaluation board which should
be set for the required operating setup before using the board.
The function of this link option is described below.
LK1
Function
This option is used to control the selectable
regulator on the AD421 that is used to power
the AD421 itself and the digital buffers on the
board.
Position
A
B
C
Function
With this link in position A, the LV pin on the
AD421 is connected to COM, in this position
the regulated voltage for the AD421 and the
digital buffer is set to 5V.
With this link in position B, the LV pin on the
AD421 is connected to V_CC, in this position the
regulated voltage for the AD421 and the digital
buffer/level shifter is set to 3V.
With this link in position C, the LV pin on the
AD421 is connected through a 0.01uF capacitor
to V_CC, in this position the regulated voltage for
the AD421 and the digital buffer/level shifter is
set to 3.3V.
EVALUATION BOARD INTERFACING
Interfacing to the evaluation board is via a 36-pin Centronics
connector, SKT1 using a standard parallel printer port cable.
The pinout for the SKT1 connector is given in Figure 1 and its
corresponding pin designations are given in Table I. The
evaluation board should be powered up before a cable is
connected to the connector.
The digital interface on the AD421 consists of just three wires:
DATA, CLOCK and LATCH. The interface connects directly
to the serial ports of commonly-used microcontrollers without
the need for any external glue logic. On this evaluation board
the PC via the printer port is used to emulate a microcontroller.
Data is loaded MSB first into the input shift register of the
AD421 on the rising edge of the CLOCK signal and is trans-
ferred to the DAC latch on the rising edge of the LATCH
signal. This data can take two forms; normal 4-20mA data and
alarm current data. The first form is where the AD421 operates
over its normal 4mA to 20mA output range with 16-bits of
resolution between these end-points. The second form allows
the user to program a current value outside this range as an
indication from the transmitter than there is a problem with the
transducer i.e. tranducer burnout. The AD421 counts the
number of clock pulses which it receives between LATCH
signals as a means of determining whether the data clocked in is
4-20mA data or alarm current data.
If there are 16 rising clock edges between successive LATCH
pulses then the data to be loaded to the input shift register is
assumed to be normal 4-20mA data.
If there are more than 16 rising clock pulses between successive
LATCH pulses then the data to be loaded to the input shift
register is assumed to be alarm current data.
Table I. SKT1 Pin Designations
1
NC
2
NC
3
LATCH
4
NC
5
CLOCK
6-8 NC
9
DATA
10-18 NC
19-25 DGND
26-36 NC
No Connect. This pin is not connected
on the evaluation board.
No Connect. This pin is not connected
on the evaluation board.
Latch Input. The signal on this pin is
buffered in 5V operating mode and
level translated in both 3.3V and 3V
modes using a 74HC4050 before being
applied to the LATCH pin of the
AD421. On the rising edge of the latch
signal data is loaded from the input
register to the DAC register and the
DAC output is updated.
No Connect. This pin is not connected
on the evaluation board.
Serial Clock. The signal on this pin is
buffered when using a V_CC of 5V and
level translated when V_CC is 3.3V or 3V
before being applied to the CLOCK
pin of the AD421. Data on the DATA
pin is clocked into the AD421 shift reg-
ister on the rising edge of this clock in-
put.
No Connect. These pins are not con-
nected on the evaluation board.
Serial Data Input. Data applied to this
pin is buffered when using a V_CC of 5V
and level translated when V_CC is 3.3V
or 3V before being applied to the
AD421's DATA pin. The serial data
applied to the DATA pin is written to
the input shift register on the part. Data
from this input shift register is trans-
ferred to the data register on the rising
edge of the LATCH signal.
No Connect. These pins are not con-
nected on the evaluation board.
Ground reference point for digital input
signals. Connects to the COM plane on
the evaluation board.
No Connect. These pins are not con-
nected on the evaluation board.
18
1
36
19
Figure 1. SKT1 Pin Configuration, Pin View.
–2–
REV. A