CN0388 Datasheet, PDF (2/5 Pages) Analog Devices – Devices Connected

CN-0388
Circuit Note
ADA4899-1
ADN4651 (×2)
D±
100Ω
100Ω D±
AD7960
CLK± _100Ω
DCO±
100Ω
100Ω
CLK±
XILINX
SPARTAN 6
FPGA
100Ω DCO±
ADA4899-1
CNV± 100Ω
EN0 TO EN3
100Ω
ADuM4400 (×2)
EN0₁ TO EN3₁
EN0₂ TO EN3₂
CNV±
LDO ENABLE
PG_C2M₁
GA0₁, GA1₁
PG_C2M₂
GA0₂, GA1₂
EVAL-AD7960FMCZ
GA0, GA1
SDP ID
EEPROM
SDA
SCL
ADuM2251
SDA₁
SDA₂
SCL₁
EVAL-CN0388-FMCZ
SCL₂
ADSP-BF527
EVAL-SDP-CH1Z
+12V DC
Figure 1. EVAL-AD7960FMCZ and EVAL-SDP-CH1Z Isolated with ADN4651 EVAL-CN0388-FMCZ Interposer Board
+12V DC
USB
(PC)
CIRCUIT DESCRIPTION
The interposer circuit relies upon two ADN4651 600 Mbps LVDS
isolators to isolate the LVDS interface to the AD7960. As shown
in Figure 1, two LVDS clocks are sent from the Spartan 6 FPGA
to the AD7960; the 5 MHz sample clock (CNV±) and a 300 MHz
reference clock (CLK±). The AD7960 uses the 300 MHz reference
to clock out bursts of sample data at 600 Mbps on D±, synchronous
with an echoed 300 MHz clock (DCO±). D± is idle after each
data burst to avoid interfering with the acquisition phase of the
converter. The ADN4651 houses a pair of bidirectional digital
isolators that integrate Analog Devices, Inc., iCoupler® technology
to operate at high speed with very low jitter. The VIN+ and VIN−
ac voltage inputs are passed through two separate ADA4899-1
unity-gain stable voltage feedback op amps to which their
corresponding outputs are fed into the AD7960. The differential
signal of the two input signals then undergoes analog-to-digital
conversion and is sent out via D±, synchronized to DCO±.
EEPROM clock (SCL) and data (SDA) from the Blackfin ADSP-
BF527 interface.
Communications between the Blackfin ADSP-BF527 and
Spartan 6 FPGA to the interposer and measurement circuits are
controlled through the USB port on the EVAL-SDP-CH1Z to
the evaluation software installed on a PC as shown in Figure 1.
The circuit is powered on the logic and bus side by two 12 V dc
supplies, where four supply rails are generated on the EVAL-
AD7960FMCZ and three supply rails are generated on the
EVAL-CN0388-FMCZ. On the EVAL-AD7960FMCZ, the
ADP7104 CMOS LDO produces 5 V, the ADP7102 CMOS
LDO produces 7 V, the ADP2300 nonsynchronous step-down
regulator produces −2.5 V, and the ADP124 CMOS linear
regulator produces 1.8 V. On the EVAL-CN0388-FMCZ, the
ADP3335 produces 5 V, the ADP151 linear regulator (2.5 V
version) produces 2.5 V, and the ADP151 linear regulator (3.3 V
version) produces 3.3 V.
The Blackfin® ADSP-BF527 outputs the appropriate logic
high and logic low levels using 1.8 V logic only through the
ADuM4400 quad digital isolators to the AD7960 enable pins
(EN0 to EN3), as well as the on-board LDO enable (PC_C2M)
and the SDP ID EEPROM address (GA0, GA1). The enable pins
on the AD7960 can be configured to specific operational
requirements. Full information is available in the AD7960 data
sheet. The ADuM2251 dual I²C isolator isolates the SDP ID
As shown in Figure 1, termination resistors of 100 Ω are fitted
on each LVDS input and output of the two ADN4651 isolators
at CNV±, CLK±, D±, and DCO± (R11, R12, R13, and R14).
Power and ground on both the logic and bus sides are
connected via a barrel connector. Logic levels, clocks, and data
signals are connected throughout the EVAL-AD7960FMCZ,
EVAL-CN0388-FMCZ, and EVAL-SDP-CH1Z via traces to
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