CN-0174 Datasheet, PDF (2/3 Pages) Analog Devices – Low Noise, 12 GHz, Microwave Fractional-N Phase-Locked Loop Using an Active Loop Filter and RF Prescaler

CN-0174
and output rail-to-rail operation. A low noise op amp is required
because the op amp output noise will feed through to the RF
output, shaped by the active filter response. Input rail-to-rail
operation is also a very important consideration for PLL active
filters as it allows the use of a single op amp supply. This is
because the charge pump output (CPOUT) will start at 0 V on
power-up, which can cause problems for op amps that do
not have rail-to-rail input voltage ranges. This also allows the
noninverting input of the op amp to be biased at a voltage
above ground with built-in margin to any changes in the bias
voltage due to resistor mismatch or temperature change.
It is recommended to set the bias voltage level to approximately
half the charge pump supply (VP), as this meets both the input
voltage range requirements with plenty of margin and gives
best charge pump spur performance. Measurements for this
circuit note were taken with VP = 5 V and op amp common-
mode bias = 2.2 V. To help minimize any reference noise feed-
through, a large decoupling capacitor of 1µF was placed close
to the noninverting op amp input pin as shown in Figure 1.
This capacitor with the 47 kΩ resistor forms an RC filter
with a cut-off below 10 Hz.
Loop Filter Design
The PLL loop filter design was done using Analog Devices free
simulation tool, ADIsimPLL. This tool allows the design and
simulation of several passive and active PLL loop filter topologies
and has a library of Analog Devices op amps built in, which
include the important op amp specifications such as voltage and
current noise, input offset and bias currents, and voltage supply
range. The simulation tool accurately predicts PLL closed loop
phase noise and is able to model the effect of op amp noise along
with the noise of the other PLL loop components. The ADIsimPLL
simulation design file for this circuit note can be found at
www.analog.com/CN0174_ADIsimPLL.
An inverting topology with pre-filtering was chosen. Pre-filtering
is advisable so as not to overdrive the amplifier with the very
short current pulses from the charge pump—which could slew
rate-limit the input voltage. When using the inverting topology,
it is important to make sure that the PLL IC allows the PFD
polarity to be inverted, canceling out the op amp’s inversion,
and driving the VCO with the correct polarity. The ADF4156
PLL has this PD polarity option.
Setup and Measurement
The settings used for the circuit are given in Table 1. Measured
results are shown in Figure 2 versus the simulated performance
as predicted by ADIsimPLL. As can be seen the results agree
quite well. The measured integrated phase noise is 0.35 ps rms.
The measurement setup is shown in Figure 3.
Circuit Note
Table 1. Test Measurement Settings
Parameter
Value
Unit
RF Frequency
12
GHz
ADF4156 RF input frequency 3
GHz
PLL Loop Filter Bandwidth
30
kHz
Reference Input Frequency
100
MHz
PFD Frequency
25
MHz
Charge Pump Setting
5
mA
PD Polarity Bit
Negative
Noise Mode
Low Noise
The performance of this or any high speed circuit is highly
dependent on proper PCB layout. This includes, but is not
limited to, power supply bypassing, controlled impedance lines
(where required), component placement, signal routing, power
and ground planes. (See MT-031 Tutorial, MT-101Tutorial, and
article, A Practical Guide to High-Speed Printed-Circuit-Board
Layout, for more detailed information regarding PCB layout.)
–60
–70
MEASURED PHASE NOISE
–80
–90
–100
–110
ADIsimPLL
SIMULATED PHASE NOISE
–120
–130
–140
–150
–160
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET FROM CARRIER (Hz)
100M
Figure 2. Measured vs. Simulated Phase Noise Performance of the 12 GHz PLL
COMMON VARIATIONS
There are several active loop filter topologies available in
ADIsimPLL, using both inverting or non-inverting op amp
configurations. The phase noise trade-offs can be investigated
in ADIsimPLL. The inverting topology allows you to obtain
output voltages as low as the minimum output voltage of the op
amp, which can be as low as 125 mV for the OP184. In contrast
to the non-inverting topology where the output voltage is
limited to the minimum charge pump voltage (0.5 V) multiplied
by the non-inverting gain.
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