CN-0140 Datasheet, PDF (2/4 Pages) Analog Devices – High Performance, Dual Channel IF Sampling Receiver

CN-0140
Circuit Note
The RF and LO input ports are already ac-coupled to prevent
nonzero dc voltages from damaging the RF balun or LO input
circuits, which are part of the ADL5356. The ADL5356 is
configured for single-ended LO operation with a recommended
LO drive of 0 dBm. With the LOSW pin of the mixer grounded,
only one of the two LO channels (LOI2) is used in this circuit.
The mixer differential IF interface requires pull-up choke
inductors to bias the open-collector outputs and to set the
output impedance match. The shunting impedance of the choke
inductors used to couple dc current into the IF amplifier should
be selected to provide the desired output return loss. The real
part of the mixer output impedance is approximately 200 Ω,
which matches many commonly used SAW filters without the
need for a transformer.
The receiver channel filtering is mainly performed by a
153.6 MHz, 20 MHz bandwidth Epcos model B5206 SAW filter
which follows the mixer. The typical insertion loss (IL) of this
filter is about 9 dB. The natural matched impedance of this
SAW filter is 100 Ω differential. A simple L-C reactive network
matches the SAW filter to the mixer 200 Ω differential output
and the AD8376 VGA 150 Ω differential input impedance.
Table 1 highlights the cascaded performance of the dual mixer
plus SAW filter. Note that IP3 is the third-order intercept point;
IP1dB is the input referred −1 dB compression point; and NF is
the noise figure.
A receiver gain control of 24 dB is provided by the AD8376
dual, high output linearity VGA that is optimized for ADC
interfacing. Two independent 5-bit binary codes change each
attenuator setting in 1 dB steps such that the gain of each
amplifier can be set from +20 dB to −4 dB. The output third
order intercept point ( IP3) and noise floor essentially remain
constant across the 24 dB available gain range. This is a valuable
feature in a variable gain receiver where it is desirable to
maintain a constant instantaneous dynamic range as the
receiver gain is modified. The output IP3 of the AD8376 and
the subsequent antialiasing filter is in excess of 50 dBm with a
2 V p-p composite signal.
The AD8376 provides a 150 Ω input impedance and is tuned to
drive a 150 Ω load impedance. The open-collector output
structure requires dc bias through an external bias network. A
set of 1 μH choke inductors are used on each channel output to
provide bias to the open-collector output pins. An optimized
differential fourth order band-pass antialiasing filter is
implemented at the DGA outputs before analog-to-digital
conversion. Note that the antialiasing filter is terminated with
shunt input and output resistances of about 300 Ω. The shunt
resistances at either end of the filter, 309 Ω at the input and
330 Ω (through two 165 Ω bias setting resistors) at the output,
combine to present the AD8376 with a nominal 150 Ω load
impedance.
The band-pass antialiasing attenuates the output noise of the
AD8376 outside of the intended Nyquist zone. In general, the
SNR improves several dB by including a reasonable order
antialiasing filter. The antialiasing filter is comprised of a fourth
order Butterworth filter with a resonant tank circuit. The
resonant tank helps ensure that the ADC input looks like a real
resistance at the target center frequency by resonating out the
capacitive portion of the ADC load (see AN-742 and AN-827
application notes). In addition, the ac-coupling capacitors and
the bias chokes introduce additional zeros into the transfer
function. The overall frequency response takes on a band-pass
characteristic, helping to reject noise outside of the intended
Nyquist zone. The filter provides a 20 MHz pass band centered
at 153.6 MHz with 0.3 dB flatness and an insertion loss of
about 3 dB.
The ADC utilized is the 14-bit AD9258, which samples at rates
up to 125 MSPS. The AD9258’s analog inputs are driven by the
AD8376 through the band-pass antialiasing filter. The ADC
sampling rate is set to 122.88 MSPS with a full-scale input range
of 2 V p-p. The AD9258 differential clock signal is provided by
the AD9517-4, a clock generation IC with on-chip VCO. The
LVPECL level output, OUT0, is used for low jitter. The
AD9517-4 uses its internal VCO frequency of 1474.56 MHz to
derive the 122.88 MHz output clock to the ADC. A loop filter,
designed with the ADISimCLK simulation software, provides
a 60 kHz cutoff frequency and 50° of phase margin, giving
timing jitter of about 160 fs rms. This jitter corresponds to a
theoretical SNR of 76 dB, assuming a 153.6 MHz input, using
the formula SNR = 20 log(1/2π × fIN × tj).
Using this circuit, exceptional SFDR performance of
79.61 dBc at 153.6 MHz is achieved at maximum gain,
as shown in Figure 2.
Table 1. Cascaded performance of the dual mixer plus SAW filter (RF =1950 MHz, LO = 1796.4 MHz, IF = 153.6 MHz,
RF power = −10 dBm, LO power = 0 dBm)
Gain (dB)
IP3 (dBm)
IP1dB (dBm)
NF (dB)
ADL5356
8.2
30.0
11.5
9.7
ADL5356 + SAW
−0.3
28.6
11.7
10.9
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