AD8303ARZ Datasheet, PDF (2/16 Pages) Analog Devices – +3 V, Dual, Serial Input Complete 12-Bit DAC

AD8303–SPECIFICATIONS
+3 V OPERATION (@ VDD = +2.7 V to +3.6 V, –40؇C ≤ TA ≤ +85؇C, unless otherwise noted)
Parameter
Symbol Condition
Min Typ¹ Max Units
STATIC PERFORMANCE
Resolution²
Relative Accuracy²
Differential Nonlinearity²
Differential Nonlinearity²
Zero-Scale Error
Full-Scale Voltage³
Full-Scale Tempco^{3, 4}
ANALOG OUTPUTS
Output Current
Output Resistance to GND
Capacitive Load⁴
REFERENCE OUTPUT
Output Voltage
N
INL
DNL
DNL
V_ZSE
V_FS
TCV_FS
I_OUT
R_OUT
C_L
V_REF
Monotonic, T_A = +25°C
Monotonic
Data = 000_H
Data = FFF_H2
Data = 800_H, ∆V_OUT < 3 mV
Data = 000_H
No Oscillation³
Load > 1 MΩ
12
Bits
–2 ±1/2 +2 LSB
–3/4 ±1/4 +3/4 LSB
–1 ±1/2 +1 LSB
1.25 +4.5 mV
2.039 2.0475 2.056 Volts
16
ppm/°C
±3 mA
30
Ω
500
pF
1
V
LOGIC INPUTS
Logic Input Low Voltage
V_IL
Logic Input High Voltage
V_IH
Input Leakage Current
I_IL
Input Capacitance⁴
C_IL
INTERFACE TIMING SPECIFICATIONS^{4, 5}
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Reset Pulse Width
Load Setup
Load Hold
Select
Deselect
t_CH
t_CL
t_LDW
t_DS
t_DH
t_RS
t_LD1
t_LD2
t_CSS
t_CSH
AC CHARACTERISTICS⁴
Voltage Output Settling Time⁶
t_S
Voltage Output Settling Time⁶
t_S
Shutdown Recovery Time
t_DSR
Output Slew Rate
SR
DAC Glitch
Q
Digital Feedthrough
Q
To ±0.1% of Full Scale
To ±1 LSB of Final Value
To ±0.1% of Full Scale
Data = 000_H to FFFH to 000_H
0.6 V
2.1
V
10 µA
10 pF
40
ns
40
ns
40
ns
15
ns
15
ns
40
ns
15
ns
40
ns
40
ns
40
ns
4
µs
14
µs
10
µs
2.0
V/µs
15
nV/s
15
nV/s
SUPPLY CHARACTERISTICS
Power Supply Range
Shutdown Current
Supply Current⁷
Power Dissipation
Power Supply Sensitivity
V_{DD RANGE} DNL < ± 1 LSB
2.7
I_{DD_SD}
SHDN = 0, No Load, V_IL = 0 V, T_A = +25°C
I_DD
V_DD = 3 V, V_IL = 0 V, No Load
P_DISS
V_DD = 3 V, V_IL = 0 V, No Load
PSS
∆V_DD = ± 5%
0.02
2
6
0.001
5.5 V
1 µA
3.2 mA
9.6 mW
0.004 %/%
NOTES
1_{Typical readings represent the average value of room temperature operation.}
2_{1 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000 H, 001H) are excluded from the linearity error measurement.}
3_{Includes internal voltage reference error.}
4_{These parameters are guaranteed by design and not subject to production testing.}
5_{All input control signals are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.}
6_{The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground.}
7_{See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels.}
Specifications subject to change without notice.
–2–
REV. 0