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AD561 Datasheet, PDF (2/8 Pages) Analog Devices – Low Cost 10-Bit Monolithic D/A Converter | |||
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AD561âSPECIFICATIONS (TA = +25ØC, VCC = â15 V, unless otherwise noted.)
Model
AD561J
Min
Typ
Max
AD561K
Min
Typ
Max
RESOLUTION
ACCURACY (Error Relative
to Full Scale)
DIFFERENTIAL NONLINEARITY
DATA INPUTS
TTL, VCC = +5 V
Bit ON Logic â1â
Bit OFF Logic â0â
CMOS, 10 V ⤠VCC ⤠16.5 V
Bit ON Logic â 1 â
Bit OFF Logic â0â
Logic Current (Each Bit) (TMIN to TMAX)
Bit ON Logic â1â
Bit OFF Logic â0â
OUTPUT
Current
Unipolar
Bipolar
Resistance (Exclusive of
Application Resistors)
Unipolar Zero (All Bits OFF)
Capacitance
Compliance Voltage
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON
POWER REQUIREMENTS
VCC, +4.5 V dc to +16.5 V dc
VEE, â10.8 V dc to â16.5 V dc
POWER SUPPLY GAIN SENSITIVITY
VCC, +4.5 V dc to +16.5 V dc
VEE, â10.8 V dc to â16.5 V dc
TEMPERATURE RANGE
Operating
Storage (âDâ Package)
(âNâ Package)
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero
Bipolar Zero
Full Scale
Differential Nonlinearity
MONOTONICITY
PROGRAMMABLE OUTPUT
RANGES
CALIBRATION ACCURACY
Full-Scale Error with Fixed 25 ⦠`
Resistor
Bipolar Zero Error with Fixed 10 â¦
Resistor
CALIBRATION ADJUSTMENT
RANGE
Full Scale (With 50 ⦠Trimmer)
Bipolar Zero (With 50 ⦠Trimmer)
NOTES
*Specifications same as AD561J specifications.
Specifications subject to change without notice.
10 Bits
± 1/4
(0.025)
± 1/2
± 1/2
(0.05)
10 Bits
± 1/8
(0.012)
± 1/4
± 1/4
(0.025)
± 1/2
+2.0
*
+0.8
*
70% VCC
*
30% VCC
*
+5
+100
â5
â25
*
*
*
*
1.5
2.0
2.4
*
*
*
± 0.75 ± 1.0
± 1.2
*
*
*
40 M
*
0.01
0.05
*
*
25
*
â2
â3
+10
*
*
*
250
*
8
10
12
16
*
*
*
*
2
10
4
25
*
*
*
*
0 to +70
â65 to +150
â25 to +85
*
*
*
*
*
*
1
10
2
20
15
80
2.5
Guaranteed Over Full Operating
Temperature Range
0 to +10
â5 to +5
1
5
2
10
15
30
2.5
Guaranteed Over Full Operating
Temperature Range
*
*
± 0.1
*
± 0.1
*
± 0.5
*
± 0.5
*
â2â
Units
LSB
% of FS
LSB
V
V
V
V
nA
µA
mA
mA
â¦
% of FS
pF
V
ns
mA
mA
ppm of FS/%
ppm of FS/%
°C
°C
°C
ppm of FS/°C
ppm of FS/°C
ppm of FS/°C
ppm of FS/°C
V
V
% of FS
% of FS
% of FS
% of FS
REV. A
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