AD2S90APZ Datasheet, PDF (2/12 Pages) Analog Devices – Low Cost, Complete 12-Bit Resolver-to-Digital Converter

AD2S90–SPECIFICATIONS (VDD = +5 V ؎ 5%, VSS = –5 V ؎ 5%, AGND = DGND = 0 V, TA = –40؇C to +85؇C unless
otherwise noted)
Parameter
Min
Typ
Max
Units Test Condition
SIGNAL INPUTS
Voltage Amplitude
Frequency
Input Bias Current
Input Impedance
Common-Mode Volts¹
CMRR
1.8
2.0
2.2
3
20
100
1.0
100
60
V rms
kHz
nA
MΩ
mV peak
dB
Sinusoidal Waveforms, Differential
SIN to SINLO, COS to COSLO
V_IN = 2 ± 10% V rms
V_IN = 2 ± 10% V rms
CMV @ SINLO, COSLO w.r.t.
AGND @ 10 kHz
REFERENCE INPUT
Voltage Amplitude
Frequency
Input Bias Current
Input Impedance
Permissible Phase Shift
1.8
2.0
3.35
3
20
100
100
–10
+10
V rms
kHz
nA
kΩ
Degrees
Sinusoidal Waveform
Relative to SIN, COS Inputs
CONVERTER DYNAMICS
Bandwidth
Maximum Tracking Rate
Maximum VCO Rate (CLKOUT)
Settling Time
1° Step
179° Step
ACCURACY
Angular Accuracy²
Repeatability³
700
840
500
2.048
2
1000
7
20
Hz
rps
MHz
ms
ms
± 10.6 + 1 LSB arc min
1
LSB
VELOCITY OUTPUT
Scaling
Output Voltage at 500 rps
Load Drive Capability
LOGIC INPUTS SCLK, CS
Input High Voltage (V_INH)
Input Low Voltage (V_INL)
Input Current (I_IN)
Input Capacitance
LOGIC OUTPUTS DATA, A, B,⁴
NM, CLKOUT, DIR
Output High Voltage
Output Low Voltage
SERIAL CLOCK (SCLK)
SCLK Input Rate
120
± 2.78
3.5
150
± 3.33
180
± 4.17
± 250
1.5
10
10
4.0
1.0
0.4
2
rps/V dc
V dc
µA
V_OUT = ± 2.5 V dc (typ), R_L ≥ 10 kΩ
V dc
V dc
µA
pF
V_DD = +5 V dc, V_SS = –5 V dc
V_DD = +5 V dc, V_SS = –5 V dc
V dc
V dc
V dc
MHz
V_DD = +5 V dc, V_SS = –5 V dc
I_OH = 1 mA
I_OL = 1 mA
I_OL = 400 µA
NORTH MARKER CONTROL (NMC)
90°
180°
360°
+4.75
–0.75
–4.75
POWER SUPPLIES
V_DD
V_SS
I_DD
I_SS
+4.75
–4.75
NOTES
1_{If the tolerance on signal inputs = ± 5%, then CMV = 200 mV.}
2_{1 LSB = 5.3 arc minute.}
3_{Specified at constant temperature.}
4_{Output load drive capability.}
Specifications subject to change without notice.
+5.0
DGND
–5.0
+5.25
+0.75
–5.25
+5.00
–5.00
+5.25
–5.25
10
10
V dc
North Marker Width Relative to
V dc
“A” Cycle
V dc
V dc
V dc
mA
mA
–2–
REV. D