AD28MSP01 Datasheet, PDF (2/28 Pages) Analog Devices – PSTN Signal Port

AD28msp01
V_FB
V_IN
V_OUT+
V_OUT–
16-BIT SIGMA-DELTA ADC
INPUT
AMP
ANALOG
1
SIGMA-DELTA
MODULATOR
DIGITAL 16
DECIMATION
FILTER
DIGITAL
16
ANTI-ALIASING
LOW-PASS FILTER
DIGITAL
16
HIGH-PASS
FILTER
1.728 MHz
28.8/32.0/38.4 kHz
7.2/8.0/9.6 kHz
7.2/8.0/9.6 kHz
SDOFS
SDO
500kΩ
VOLTAGE
REFERENCE
RESAMPLING
INTERPOLATION
FILTER
OUTPUT
DIFF.
AMP
TSYNC
ANALOG
SMOOTHING
FILTER
16-BIT SIGMA-DELTA DAC
1
DIGITAL
16
SIGMA-DELTA
MODULATOR
DIGITAL
16
INTERPOLATION
FILTER
DIGITAL
ANTI-IMAGING
16
LOW-PASS
FILTER
1.728 MHz
1.728 MHz
28.8/32.0/38.4 kHz
7.2/8.0/9.6 kHz
INTERNAL CLOCK
CLOCK GENERATION
CONTROL CIRCUITRY
AND
SEQUENCER
CONTROL
REGISTERS
SERIAL
PORT
SCLK
SDI
SDIFS
t_CONV t_BAUD t_BIT
r_CONV r_BAUD r_BIT
M_CLK
RESET
CS
Figure 1. AD28msp01 Block Diagram
PIN DESCRIPTIONS
Name Type Description
Name Type Description
Analog Interface
V_IN
I Analog input to the inverting terminal of the
input amplifier.
V_FB
O
V_OUTP O
Feedback terminal of the input amplifier.
Analog output from the noninverting terminal
of the output differential amplifier.
V_OUTN O
Analog output from inverting terminal of the
output differential amplifier.
Serial Interface
SCLK O/Z Serial clock used for clocking data or control
bits to/from the serial port (SPORT). The
frequency of this clock is 1.7280 MHz. This
pin is 3-stated when the CS is low.
SDI
I Serial data input of the SPORT. Both data
and control information are input on this pin.
This pin is ignored when CS is low.
SDO O/Z Serial data output of the SPORT. Both data
and control information are output on this
pin. This pin is 3-stated when CS is low.
SDIFS I Framing synchronization signal for serial data
transfers to the AD28msp01 (via the SDI
pin). This pin is ignored when CS is low.
SDOFS O/Z Framing synchronization signal for serial data
transfers from the AD28msp01 (via the SDO
pin). This pin is 3-stated when CS is low.
Clock Generation
TSYNC I Transmit synchronization clock. This signal is
used to synchronize the transmit clocks and
the converter clocks to an external terminal/
bit-rate clock. It is used in the V.32 TSYNC
and Asynchronous TSYNC modes and is
ignored in other operating modes. The
frequency of the external clock must be
programmed in Control Register 0. This pin
must be tied high or low if it is not being
used.
TBIT O Transmit bit rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
TBAUD O Transmit baud rate clock. This is an output
clock whose frequency is programmable via
Control Register 3. It is synchronized with
the TCONV clock.
–2–
REV. A