ADUCM320 Datasheet, PDF (19/31 Pages) Analog Devices – Fully differential and single-ended modes

ADuCM320
Table 7. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
Description
t_CS
CS to SCLK edge
t_CSM
CS high time between active periods
tSL
SCLK low pulse width
tSH
SCLK high pulse width
tDAV
Data output valid after SCLK edge
tDSU
Data input setup time before SCLK edge
tDHD
Data input hold time after SCLK edge
tDF
Data output fall time
tDR
Data output rise time
tSR
SCLK rise time
tSF
SCLK fall time
tSFS
CS high after SCLK edge
t_CSM
CS
SCLK
(POLARITY = 0)
t_CS
t_SH
SCLK
(POLARITY = 1)
MISO
t_DAV
t_SL
t_DF
MSB
Min
10
SCLKx
10
10
1
1
20
Typ
(SPIDIV + 1) × tHCLK
(SPIDIV + 1) × tHCLK
20
25
25
t_SR
t_DR
BITS 6 TO 1
t_SFS
t_SF
LSB
MOSI
MSB IN
BITS 6 TO 1
t_DSU
t_DHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
LSB IN
Data Sheet
Max Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. C | Page 18 of 30