ADSP-2189MBSTZ-266 Datasheet, PDF (19/32 Pages) Analog Devices – DSP Microcomputer

ADSP-2189M
TIMING PARAMETERS
Parameter
Min
Clock Signals and Reset
Timing Requirements:
t_CKI
t_CKIL
t_CKIH
CLKIN Period
26.6
CLKIN Width Low
13
CLKIN Width High
13
Max
Unit
80
ns
ns
ns
Switching Characteristics:
t_CKL
CLKOUT Width Low
0.5t_CK – 2
ns
t_CKH
CLKOUT Width High
0.5t_CK – 2
ns
t_CKOH
CLKIN High to CLKOUT High
0
13
ns
Control Signals
Timing Requirements:
t_RSP
RESET Width Low
5t_CK1
ns
t_MS
Mode Setup before RESET High
2
ns
t_MH
Mode Hold after RESET High
5
ns
NOTE
1_{Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal}
oscillator start-up time).
t_CKI
t_CKIH
CLKIN
CLKOUT
t_CKIL
t_CKOH
t_CKH
t_CKL
PF(3:0)*
RESET
t_MS
t_MH
*PF3 IS MODE D, PF2 IS MODE C, PF0 IS MODE A
Figure 22. Clock Signals
REV. A
–19–