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ADE7858 Datasheet, PDF (19/76 Pages) Analog Devices – Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
Preliminary Technical Data
ADE7858
THEORY OF OPERATION
ANALOG INPUTS
The ADE7858 has six analog inputs forming current and
voltage channels. The current channels consist of four pairs of
fully differential voltage inputs: IAP and IAN, IBP and IBN and
ICP and ICN. These voltage input pairs have a maximum
differential signal of ±0.5 V. In addition, the maximum signal
level on analog inputs for IxP/IxN is ±0.5 V with respect to
AGND. The maximum common mode signal allowed on the
inputs is ±25 mV. Figure 9 presents a schematic of the current
channels inputs and their relation to the maximum common
mode voltage.
All inputs have a programmable gain amplifier (PGA) with
possible gain selection of 1, 2, 4, 8 or 16. The gain of IA, IB and
IC inputs is set in bits 2-0 (PGA1) of GAIN[15:0] register. See
Table 35 for details on GAIN[15:0] register.
The voltage channel has three single-ended voltage inputs: VAP,
VBP and VCP. These single-ended voltage inputs have a
maximum input voltage of ±0.5 V with respect to VN. In
addition, the maximum signal level on analog inputs for VxP
and VN is ±0.5 V with respect to AGND. The maximum
common mode signal allowed on the inputs is ±25 mV. Figure
11 presents a schematic of the voltage channels inputs and their
relation to the maximum common mode voltage.
All inputs have a programmable gain with possible gain
selection of 1, 2, 4, 8, or 16. The setting is done using bits 8-6
(PGA3) in GAIN[15:0] register – see Table 35.
Figure 10 shows how the gain selection from GAIN[15:0]
register works in both current and voltage channels.
V1+V2
+500mV
VCM
-500mV
DIFFERENTIAL INPUT
V1+V2=500mV MAX PEAK
COMMON MODE
VCM=+/-25mV MAX
+
IAP, IBP or
-
V1
ICP
+
+
- VCM
+
-
V2
-
IAN, IBN
or ICN
clock. In the ADE7858, the sampling clock is equal to
1.024MHz (CLKIN/16). The 1-bit DAC in the feedback loop is
driven by the serial data stream. The DAC output is subtracted
from the input signal. If the loop gain is high enough, the
average value of the DAC output (and therefore the bit stream)
can approach that of the input signal level. For any given input
value in a single sampling interval, the data from the 1-bit ADC
is virtually meaningless. Only when a large number of samples
are averaged is a meaningful result obtained. This averaging is
carried out in the second part of the ADC, the digital low-pass
filter. By averaging a large number of bits from the modulator,
the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
IxP, VxP
GAIN
SELECTION
VIN
K x VIN
IxN, VN
x=A,B,C
Figure 10. PGA in current and voltage channels
DIFFERENTIAL INPUT
V1+V2=500mV MAX PEAK
COMMON MODE
V1
VCM=+/-25mV MAX
+500mV
VCM
-500mV
+
VAP, VBP
-
V1
or VCP
+
-
+
VN
-
VCM
Figure 11. Maximum input level, voltage channels, Gain=1
ANALOG
LOW-PASS FILTER
R
C
CLKIN/16
INTEGRATOR
+
LATCHED
+ COMPARATOR
–
–
VREF
DIGITAL
LOW-PASS
FILTER
24
Figure 9. Maximum input level, current channels, Gain=1
ANALOG TO DIGITAL CONVERSION
.....10100101.....
1-BIT DAC
The ADE7858 has six sigma-delta Analog to Digital Converters
(ADC). In PSM0 mode, all ADCs are active. In PSM3 mode,
the ADCs are powered down to minimize power consumption.
For simplicity, the block diagram in Figure 12 shows a first-
order -Δ ADC. The converter is made up of the -Δ
modulator and the digital low-pass filter.
Figure 12. First-Order -∆ ADC
The -Δ converter uses two techniques to achieve high
resolution from what is essentially a 1-bit conversion technique.
The first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency), which is many times higher than
the bandwidth of interest. For example, the sampling rate in the
A -Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
ADE7858 is 1.024MHz and the bandwidth of interest is 40 Hz
to 2 kHz. Oversampling has the effect of spreading the
Rev. PrA | Page 19 of 76