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ADAS3023 Datasheet, PDF (19/32 Pages) Analog Devices – 16-Bit, 8-Channel Simultaneous Sampling Data Acquisition System
Data Sheet
ADAS3023
THEORY OF OPERATION
OVERVIEW
The ADAS3023 is a 16-bit, 8-channel simultaneous system on a
single chip that integrates the typical components used in a data
acquisition system in one easy to use, programmable device. It is
capable of converting two channels simultaneously up to 500,000
samples per second (500 kSPS) throughput. The ADAS3023
features
• High impedance inputs
• High common-mode rejection
• An 8-channel, low leakage track and hold
• A programmable gain instrumentation amplifier (PGIA)
with four selectable differential input ranges from ±2.56 V
to ±20.48 V
• A 16-bit PulSAR® ADC with no missing codes
• An internal, precision, low drift 4.096 V reference and
buffer
The ADAS3023 uses the Analog Devices patented high voltage
iCMOS process allowing up to a ±20.48 V differential input voltage
range when using ±15 V supplies, which makes the device suitable
for industrial applications.
The device is housed in a small 6 mm × 6 mm, 40-lead LFCSP
package and can operate over the industrial temperature range of
−40°C to +85°C. A typical discrete multichannel data acquisition
system containing similar circuitry requires more space on the
circuit board than the ADAS3023. Therefore, advantages of the
ADAS3023 solution include a reduced footprint and less complex
design requirements, leading to faster time to market and lower costs.
OPERATION
The analog circuitry of the ADAS3023 consists of a high
impedance, low leakage, track-and-hold PGIA with a high
common-mode rejection that can accept the full-scale differ-
ential voltages of ±2.56 V, ±5.12 V, ±10.24 V, and ±20.48 V (see
Figure 15). The ADAS3023 can be configured to sample two,
four, six, or eight channels simultaneously.
The ADAS3023 offers true high impedance inputs in a differential
structure and rejects common-mode signals present on the inputs.
This architecture does not require additional input buffers (op
amps) that are usually required for signal buffering, level shifting,
amplification, attenuation, and kickback reduction when using
switched capacitor-based SAR ADCs.
Digital control of the programmable gain setting of each
channel input is set via the configuration (CFG) register.
The conversion results are output in twos complement format
on the serial data output (SDO) and through an optional secondary
serial data output on the BUSY/SDO2 pin. The digital interface
uses a dedicated chip select (CS) to control data access to and
from the ADAS3023 together with a BUSY/SDO2 output, asyn-
chronous reset (RESET), and power-down (PD) inputs.
The internal reference of the ADAS3023 uses an internal temper-
ature compensated 2.5 V output band gap reference, followed by
a precision buffer amplifier to provide the 4.096 V high precision
system reference.
All of these components are configured through a serial (SPI-
compatible), 16-bit CFG register. Configuration and conversion
results are read after the conversions are completed.
The ADAS3023 requires a minimum of three power supplies
+15 V, −15 V, and +5 V. Internal low dropout regulators provide
the necessary 2.5 V system voltages that must be decoupled
externally via dedicated pins (ACAP, DCAP, and RCAP). The
ADAS3023 can be interfaced to any 1.8 V to 5 V digital logic
family using the dedicated VIO logic level voltage supply (see
Table 9).
A rising edge on the CNV pin initiates a conversion and changes
the ADAS3023 from track to hold. In this state, the ADAS3023
performs the analog signal conditioning and conversion. When
the signal conditioning is completed, the ADAS3023 returns to
the track state while, at the same time, quantizes the sample. This
two-tiered process satisfies the necessary settling time requirement
and achieves a fast throughput rate of up to 500 kSPS with 16-bit
accuracy.
DIFF TO
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
VDDH AVDD DVDD VIO
RESET
PD
TRACK
AND
HOLD
PGIA
LOGIC/
INTERFACE
PulSAR
ADC
ADAS3023
BUF
REF
VSSH AGND DGND REFx
Figure 35. Simplified Block Diagram
CNV
BUSY
CS
SCK
DIN
SDO
REFIN
Rev. 0 | Page 19 of 32