ADA4522-2 Datasheet, PDF (19/30 Pages) Analog Devices – 55 V, EMI Enhanced, Zero Drift, Ultralow Noise, Rail-to-Rail Output Operational Amplifier

Data Sheet
+1V
0
INPUT
–1V
V_SY = ±2.5V
R_L = 10kΩ
C_L = 50pF
DUT A_V = –1
OUTPUT
+10mV
0
–10mV
ERROR BAND
POST GAIN = 10
TIME (2µs/DIV)
Figure 65. Negative Settling Time to 0.1%, V_SY = ±2.5 V
+5V
0
INPUT
–5V
V_SY = ±15V AND ±27.5V
R_L = 10kΩ
C_L = 50pF
DUT A_V = –1
OUTPUT
+50mV
ERROR BAND
POST GAIN = 10
0
–50mV
TIME (4µs/DIV)
Figure 66. Negative Settling Time to 0.1%, V_SY = ±15 V and ±27.5 V
60
V_IN = ±26V
V_SY = ±27.5V
50
R_L = 10kΩ
A_V = –1
40
30
V_IN = ±13.5V
V_SY = ±15V
20
10
V_IN = ±1V
V_SY = ±2.5V
0
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 67. Output Voltage Swing vs. Frequency
ADA4522-2/ADA4522-4
INPUT
+1V
0
–1V
OUTPUT
V_SY = ±2.5V
R_L = 10kΩ
C_L = 50pF
DUT A_V = –1
+10mV
0
–10mV
ERROR BAND
POST GAIN = 10
TIME (2µs/DIV)
Figure 68. Positive Settling Time to 0.1%, V_SY = ±2.5 V
+5V
0
INPUT
–5V
V_SY = ±15V AND ±27.5V
R_L = 10kΩ
C_L = 50pF
DUT A_V = –1
OUTPUT
+50mV
ERROR BAND
POST GAIN = 10
0
–50mV
TIME (4µs/DIV)
Figure 69. Positive Settling Time to 0.1%, V_SY = ±15 V and ±27.5 V
Rev. B | Page 19 of 30