AD9865 Datasheet, PDF (19/48 Pages) Analog Devices – Broadband Modem Mixed-Signal Front End

AD9865
SERIAL PORT
Table 10. SPI Register Mapping
Address
(Hex)¹
Bit
Break-
down
Description
Width
Power-Up Default Value
MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex)
CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1
SPI PORT CONFIGURATION AND SOFTWARE RESET
0x00
(7)
4-Wire SPI
1
0
0
0
0
(6)
LSB First
1
0
0
0
0
(5)
S/W Reset
1
0
0
0
0
POWER CONTROL REGISTERS (via PWR_DWN pin)
0x01
(7)
Clock Syn.
1
0
0
0
0
(6)
TxDAC/IAMP
1
0
0
0
0
(5)
Tx Digital
1
0
0
0
0
(4)
REF
1
0
0
0
0
(3)
ADC CML
1
0
0
0
0
(2)
ADC
1
0
0
0
0
(1)
PGA Bias
1
0
0
0
0
(0)
RxPGA
1
0
0
0
0
0x02
(7)
CLK Syn.
1
0
0
0
1*
(6)
TxDAC/IAMP
1
1
1
1
1
(5)
Tx Digital
1
1
1
1
1
(4)
REF
1
1
1
1
1
(3)
ADC CML
1
1
1
1
1
(2)
ADC
1
1
1
1
1
(1)
PGA Bias
1
1
1
1
1
(0)
RxPGA
1
1
1
1
1
HALF-DUPLEX POWER CONTROL
0x03
(7:3) Tx OFF Delay
5
(2)
Rx _TXEN
(1)
Tx PWRDN
1
1
0xFF
0xFF
N/A
N/A
(0)
Rx PWRDN
1
PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL
0x04
(5)
Duty Cycle Enable 1
0
0
0
0
(4)
fADC from PLL
1
0
0
0
0
(3:2) PLL Divide-N
2
00
00
00
00
(1:0) PLL Multiplier-M 2
01
10*
01
01
0x05
(2)
OSCIN to RXCLK 1
0
0
0
1*
(1)
Invert RXCLK
1
0
0
0
0
(0)
Disabled RXCLK 1
0
0
0
0
0x06
(7:6) CLKOUT2 Divide 2
01
01
01
01
(5)
CLKOUT2 Invert 1
0
0
0
0
(4)
CLKOUT2 Disable 1
0
0
0
1*
(3:2) CLKOUT1 Divide 2
01
01
01
01
(1)
CLKOUT1 Invert 1
0
0
0
0
(0)
CLKOUT1 Disable 1
0
0
0
1*
Rx PATH CONTROL
0x07
(5)
Initiate Offset Cal. 1
0
0
0
0
(4)
Rx Low Power
1
0
1*
0
1*
(0)
Rx Filter ON
1
1
1
1
1
Comments
Default SPI configuration is
3-wire, MSB first.
PWR_DWN = 0.
Default setting is for all
blocks powered on.
PWR_DWN = 1.
Default setting* is for all
functional blocks powered
down except PLL.
*MODE = CONFIG = 1.
Setting has PLL powered
down with OSCIN input
routed to RXCLK output.
Default setting is for TXEN
input to control power
on/off of Tx/Rx path.
Tx driver delayed by 31
1/fDATA clock cycles.
Default setting is Duty Cycle
Restore disabled, ADC CLK
from OSCIN input, and PLL
multiplier × 2 setting.
*PLL multiplier × 4 setting.
Full-duplex RXCLK normally
at nibble rate.
*Exception on power-up.
Default setting is CLKOUT2
and CLKOUT1 enabled with
divide-by-2.
*CLKOUT1 and CLKOUT2
disabled.
Default setting has LPF ON
and Rx path at nominal
power bias setting.
*Rx path to low power.
Rev. A | Page 19 of 48