AD9683 Datasheet, PDF (19/44 Pages) Analog Devices – 14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter

Data Sheet
THEORY OF OPERATION
The AD9683 has one analog input channel and one JESD204B
output lane. The signal passes through several stages before
appearing at the output port.
The user can sample frequencies from dc to 400 MHz using
appropriate low-pass or band-pass filtering at the ADC inputs
with little loss in ADC performance. Operation above 400 MHz
analog input is permitted but occurs at the expense of increased
ADC noise and distortion.
A synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9683 are accomplished using a
3-pin, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9683 architecture consists of a front-end, sample-and-
hold circuit, followed by a pipelined switched capacitor ADC. The
quantized outputs from each stage are combined into a final 14-bit
result in the digital correction logic. The pipelined architecture
permits the first stage to operate on a new input sample, and the
remaining stages to operate on the preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage contains a differential sampling circuit that can
be ac- or dc-coupled in differential or single-ended modes. The
output staging block aligns the data, corrects errors, and passes the
data to the output buffers. The output buffers are powered from a
separate supply, allowing digital output noise to be separated from
the analog core.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9683 is a differential, switchedcapacitor
circuit that has been designed for optimum performance while
processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see the configuration shown in Figure 43).
When the input is switched into sample mode, the signal source
must be capable of charging the sampling capacitors and settling
within 1/2 clock cycle.
AD9683
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications,
reduce the shunt capacitors. In combination with the driving
source impedance, the shunt capacitors limit the input band-
width. Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article, “Transformer-
Coupled Front-End for Wideband A/D Converters,” for more
information.
BIAS
VIN+
C_PAR1
S
C_S
C_PAR2
S
C_FB
H
S
S
VIN–
C_PAR1
C_S
C_PAR2
S
S
C_FB
BIAS
Figure 43. Switched Capacitor Input
For best dynamic performance, match the source impedances
driving VIN+ and VIN− and differentially balance the inputs.
Input Common Mode
The analog inputs of the AD9683 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Configuring the input so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and is
available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically 0.5 × AVDD). Decouple
the VCM pin to ground by using a 0.1 µF capacitor, as described
in the Applications Information section. Place this decoupling
capacitor close to the pin to minimize the series resistance and
inductance between the part and this capacitor.
Differential Input Configurations
Optimum performance is achieved while driving the AD9683 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-1, ADA4938-1, and ADA4930-1 differential
drivers provide excellent performance and a flexible interface to
the ADC.
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