AD9642_15 Datasheet, PDF (19/28 Pages) Analog Devices – 14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC)

Data Sheet
AD9642
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9642.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference voltage
changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9642 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or via capacitors. These pins are biased internally
(see Figure 51) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
AVDD
CLK+
4pF
0.9V
CLK–
4pF
Figure 51. Simplified Equivalent Clock Input Circuit
Clock Input Options
The AD9642 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 52 and Figure 53 show two preferable methods for
clocking the AD9642 (at clock rates of up to 625 MHz). A low
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from
10 MHz to 200 MHz. The back-to-back Schottky diodes across
the secondary winding of the transformer limit clock excursions
into the AD9642 to approximately 0.8 V p-p differential. This
limit helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9642 while
preserving the fast rise and fall times of the signal, which are
critical for low jitter performance.
CLOCK
INPUT
390pF
Mini-Circuits^®
ADT1-1WT, 1:1Z
XFMR ^390pF
50Ω ^100Ω
390pF
SCHOTTKY
DIODES:
HSMS2822
ADC
CLK+
CLK–
Figure 52. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
390pF
25Ω
390pF
ADC
CLK+
390pF
1nF
CLK–
25Ω
SCHOTTKY
DIODES:
HSMS2822
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 54. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,
AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/
ADCLK925 clock drivers offer excellent jitter performance.
CLOCK
INPUT
CLOCK
INPUT
50kΩ
0.1µF
AD95xx,
ADCLK9xx
0.1µF PECL DRIVER
50kΩ
240Ω
0.1µF
0.1µF
240Ω
CLK+
100Ω
ADC
AD9642
CLK–
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 55. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,
AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers
offer excellent jitter performance.
CLOCK
INPUT
CLOCK
INPUT
50kΩ
0.1µF
AD95xx
0.1µF ^{LVDS DRIVER}
50kΩ
0.1µF
100Ω
0.1µF
CLK+
ADC
AD9642
CLK–
Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)
Input Clock Divider
The AD9642 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. The
duty cycle stabilizer (DCS) is enabled by default on power-up.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9642 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9642.
Rev. B | Page 19 of 28