AD9514_15 Datasheet, PDF (19/28 Pages) Analog Devices – 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

Synchronization is initiated by pulling the SYNCB pin low for a
minimum of 5 ns. The input clock does not have to be present
at the time the command is issued. The synchronization occurs
after four input clock cycles.
The synchronization applies to clock outputs:
• that are not turned OFF
• where the divider is not divide = 1 (divider bypassed)
An output with its divider set to divide = 1 (divider bypassed) is
always synchronized with the input clock, with a propagation
delay.
The SYNCB pin must be pulled up for normal operation. Do
not let the SYNCB pin float.
R_SET RESISTOR
The internal bias currents of the AD9514 are set by the
RSET resistor. This resistor should be as close as possible to
the value given as a condition in the Specifications section
(RSET = 4.12 kΩ). This is a standard 1% resistor value and
should be readily obtainable. The bias currents set by this
resistor determine the logic levels and operating conditions
of the internal blocks of the AD9514. The performance figures
given in the Specifications section assume that this resistor
value is used for RSET.
VREF
The VREF pin provides a voltage level of ⅔ VS. This voltage is
one of the four logic levels used by the setup pins (S0 to S10).
These pins set the operation of the AD9514. The VREF pin
provides sufficient drive capability to drive as many of the setup
pins as necessary, up to all on a single part. The VREF pin
should be used for no other purpose.
SETUP CONFIGURATION
The specific operation of the AD9514 is set by the logic levels
applied to the setup pins (S0 to S10). These pins use four-state
logic. The logic levels used are VS and GND, plus ⅓ VS and
⅔ VS. The ⅓ VS level is provided by the internal self-biasing on
each of the setup pins (S0 to S10). This is the level seen by a
setup pin that is left not connected (NC). The ⅔ VS level is
provided by the VREF pin. All setup pins requiring the ⅔ VS
level must be tied to the VREF pin.
V_S
60kΩ
SETUP PIN
S0 TO S10
30kΩ
AD9514
Figure 28. Setup Pin (S0 to S10) Equivalent Circuit
The AD9514 operation is determined by the combination of
logic levels present at the setup pins. The setup configurations
for the AD9514 are shown in Table 10 to Table 15. The four
logic levels are referred to as 0, ⅓, ⅔, and 1. These numbers
represent the fraction of the VS voltage that defines the logic
levels. See the setup pins thresholds in Table 6.
The meaning of some of the setup pins depends on the logic
level set on other pins. For example, the effect of the S3 to S4
pair of pins depends on whether S0 = 0. If S0 = 0, the delay
block for OUT2 is off, and the logic levels on S3 to S4 set the
phase word of the OUT2 divider. However, if S0 ≠ 0, then the
full-scale delay for OUT2 is set by the logic level on S0, and S3
to S4 sets the delay block fine adjust (fraction of full scale).
S1 and S2 together determine the logic level of each output or
whether a channel is off. An output that is set to OFF is
powered down, including the divider.
OUT0 and OUT1 are LVPECL. The LVPECL output differential
voltage (VOD) can have three possible levels: 410 mV, 790 mV,
and 960 mV (limited to the available combinations, see Table 11).
OUT2 can be set to either LVDS or CMOS levels.
S5 and S6 effect depends on S2. If S2 = 0 (OUT2 is off), S5 and
S6 set the OUT1 phase word. If S2 ≠ 0, S5 and S6 set the OUT2
divide ratio. If S2 = ⅔, then the value in S9 and S10 overrides
the divide ratio for OUT2.
S7 and S8 depend on S2 and S0. If S2 ≠ 1, these pins set the
OUT1 divide ratio. However, if S2 = 1 (OUT1 is off) and S0 ≠ 0,
S7 and S8 set the phase word for OUT2.
S9 and S10 depend on S2. If S2 ≠ ⅔, these pins set the OUT0
divide ratio. If S2 = ⅔, they set the OUT2 divide ratio,
overriding S5 and S6.
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