AD9513 Datasheet, PDF (19/28 Pages) Analog Devices – 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

Table 11. Output Delay Full Scale
S0
Delay
0
Bypass
1/3
1.8 ns
2/3
6.0 ns
1
11.6 ns
Table 12. Output Logic Configuration
S1
S2
OUT0
OUT1
0
0
OFF
LVDS
1/3
0
CMOS
CMOS
2/3
0
LVDS
LVDS
1
0
LVDS
CMOS
0
1/3
CMOS
CMOS
1/3
1/3
LVDS
LVDS
2/3
1/3
LVDS
LVDS
1
1/3
CMOS
CMOS
0
2/3
OFF
OFF
1/3
2/3
OFF
OFF
2/3
2/3
OFF
OFF
1
2/3
OFF
CMOS
0
1
LVDS
OFF
1/3
1
CMOS
OFF
2/3
1
LVDS
OFF
1
1
CMOS
OFF
OUT2
OFF
OFF
OFF
OFF
CMOS
LVDS
CMOS
LVDS
OFF
LVDS
CMOS
OFF
CMOS
LVDS
LVDS
CMOS
Table 13. OUT2 Delay or Phase
S3
S4
OUT2
Delay
(S0 ≠ 0)
0
0
0
1/3
0
1/16
2/3
0
1/8
1
0
3/16
0
1/3
1/4
1/3
1/3
5/16
2/3
1/3
3/8
1
1/3
7/16
0
2/3
1/2
1/3
2/3
9/16
2/3
2/3
5/8
1
2/3
11/16
0
1
3/4
1/3
1
13/16
2/3
1
7/8
1
1
15/16
OUT2
Phase
(S0 = 0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AD9513
Table 14. OUT2 Divide or OUT1 Phase
S5
S6
OUT2
Divide (Duty Cycle¹)
(S2 ≠ 0)
0
0
1
1/3 0
2 (50%)
2/3 0
3 (33%)
1
0
4 (50%)
0
1/3
5 (40%)
1/3 1/3
6 (50%)
2/3 1/3
8 (50%)
1
1/3
9 (44%)
0
2/3
10 (50%)
1/3 2/3
12 (50%)
2/3 2/3
15 (47%)
1
2/3
16 (50%)
0
1
18 (50%)
1/3 1
24 (50%)
2/3 1
30 (50%)
1
1
32 (50%)
OUT1
Phase
(S2 = 0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1 _{Duty cycle is the clock signal high time divided by the total period.}
Table 15. OUT1 Divide or OUT2 Phase
S7
S8
OUT1
Divide (Duty Cycle¹)
(S2 ≠ 1)
0
0
1
1/3
0
2 (50%)
2/3
0
3 (33%)
1
0
4 (50%)
0
1/3
5 (40%)
1/3
1/3
6 (50%)
2/3
1/3
8 (50%)
1
1/3
9 (44%)
0
2/3
10 (50%)
1/3
2/3
12 (50%)
2/3
2/3
15 (47%)
1
2/3
16 (50%)
0
1
18 (50%)
1/3
1
24 (50%)
2/3
1
30 (50%)
1
1
32 (50%)
OUT2 Phase
(S2 = 1 and S0 ≠ 0)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1 _{Duty cycle is the clock signal high time divided by the total period.}
Rev. 0 | Page 19 of 28