AD8318_06 Datasheet, PDF (19/24 Pages) Analog Devices – 1 MHz to 8 GHz, 60 dB Logarithmic Detector/Controller

In many log amp applications, it may be necessary to lower the
corner frequency of the postdemodulation filtering to achieve low
output ripple while maintaining a rapid response time to changes in
signal level. For an example of a 4-pole active filter, see the AD8307
data sheet.
CONTROLLER MODE
The AD8318 provides a controller mode feature at the VOUT pin.
Using VSET for the setpoint voltage, it is possible for the AD8318 to
control subsystems, such as power amplifiers (PAs), variable gain
amplifiers (VGAs), or variable voltage attenuators (VVAs) that have
output power that increases monotonically with respect to their gain
control signal.
To operate in controller mode, the link between VSET and VOUT is
broken. A setpoint voltage is applied to the VSET input; VOUT is
connected to the gain control terminal of the VGA and the detector
RF input is connected to the output of the VGA (usually using a
directional coupler and some additional attenuation). Based on the
defined relationship between VOUT and the RF input signal when the
device is in measurement mode, the AD8318 adjusts the voltage on
VOUT (VOUT is now an error amplifier output) until the level at
the RF input corresponds to the applied VSET.
When the AD8318 operates in controller mode, there is no defined
relationship between VSET and VOUT voltage; VOUT settles to a value
that results in the correct input signal level appearing at INHI/INLO.
In order for this output power control loop to be stable, a ground-
referenced capacitor is connected to the CLPF pin. This capacitor,
CFLT, integrates the error signal (in the form of a current) to set the
loop bandwidth and ensure loop stability. For further details on
control loop dynamics, refer to the AD8315 data sheet.
VGA/VVA
RFIN
DIRECTIONAL
COUPLER
ATTENUATOR
GAIN
CONTROL
VOLTAGE
1nF
VOUT
INHI
52.3Ω
AD8318
VSET
DAC
INLO
1nF
CLPF
C_FLT
Figure 41. AD8318 Controller Mode
Decreasing VSET, which corresponds to demanding a higher signal
from the VGA, tends to increase VOUT. The gain control voltage of
the VGA must have a positive sense. A positive control voltage to the
VGA increases the gain of the device.
AD8318
The basic connections for operating the AD8318 as an analog
controller with the AD8367 are shown in Figure 42. The
AD8367 is a low frequency to 500 MHz VGA with 45 dB of
dynamic range. This configuration is very similar to the one
shown in Figure 41. For applications working at high input
frequencies, such as cellular bands or WLAN, or those
requiring large gain control ranges, the AD8318 can control the
ADL5330 10 MHz to 3 GHz RF VGA. For further details and an
application schematic, refer to the ADL5330 data sheet.
The voltage applied to the GAIN pin controls the gain of the
AD8367. This voltage, VGAIN, is scaled linear-in-dB with a slope
of 20 mV/dB and runs from 50 mV at −2.5 dB of gain, up to
1.0 V at +42.5 dB.
The incoming RF signal to the AD8367 has a varying amplitude
level. Receiving and demodulating it with the lowest possible
error requires that the signal levels be optimized for the highest
signal-to-noise ratio (SNR) feeding into the analog-to-digital
converters (ADC). This is done by using an automatic gain
control (AGC) loop. In Figure 42, the voltage output of the
AD8318 modifies the gain of the AD8367 until the incoming
RF signal produces an output voltage that is equal to the
setpoint voltage VSET.
RF INPUT SIGNAL
+3V
VPOS GND
INPT
AD8367
VGA
VOUT
GAIN
HPFL
0.1μF _174Ω
57.6Ω
RF OUTPUT SIGNAL
R2
261Ω
R1 +5V
1kΩ
DAC
+V_SET
SETPOINT
VOLTAGE
C_FLT
100pF
VOUT VPOS
VSET
INHI
AD8318
INLO
CLPFGND
C_HP
100pF
R_HP
100Ω
1nF
1nF
100MHz
BANDPASS
FILTER
Figure 42. AD8318 Operating in Controller Mode to Provide Automatic Gain
Control Functionality in Combination with the AD8367
The AGC loop is capable of controlling signals over ~45 dB
dynamic range. The output of the AD8367 is designed to drive
loads ≥ 200 Ω. As a result, it is not necessary to use the 53.6 Ω
resistor at the input of the AD8318; the nominal input imped-
ance of 2 kΩ is sufficient.
If the AD8367 output drives a 50 Ω load, such as an oscilloscope
or spectrum analyzer, use a simple resistive divider network.
The divider used in Figure 42 has an insertion loss of 11.5 dB.
Figure 43 shows the transfer function of output power vs. VSET
voltage for a 100 MHz sine wave at −40 dBm into the AD8367.
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