AD7946 Datasheet, PDF (19/27 Pages) Analog Devices – 14-Bit, 500 kSPS PulSAR™ ADC in MSOP/QFN

Preliminary Technical Data
CS Mode 3-Wire with BUSY Indicator
This mode is usually used when a single AD7946 is connected
to an SPI compatible digital host having an interrupt input.
The connection diagram is shown in Figure 31 and the
corresponding timing is given in Figure 32.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7946 then enters the acquisition phase and
AD7946
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
optional 15th SCK falling edge, or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CNV
VIO
SDI AD7946 SDO
SCK
CONVERT
VIO
DIGITAL HOST
47kΩ
DATA IN
IRQ
CLK
Figure 31. ^CS Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
t_CNVH
CNV
t_CONV
ACQUISITION CONVERSION
SCK
SDO
t_CYC
t_ACQ
ACQUISITION
t_SCKL
t_SCK
1
2
t_HSDO
t_DSDO
D13
3
D12
13
14
15
t_SCKH
t_DIS
D1
D0
Figure 32. ^CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev Pr D | Page 19 of 27