AD7942 Datasheet, PDF (19/24 Pages) Analog Devices – 14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN

AD7942
CS Mode 4-Wire Without Busy Indicator
This mode is most often used when multiple AD7942s are
connected to an SPI-compatible digital host. A connection
diagram using two AD7942s is shown in Figure 34 and the
corresponding timing diagram is given in Figure 35.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers.
However, SDI must be returned high before the minimum
conversion time elapses and held high until the maximum
conversion time is completed to avoid generating the busy
signal indicator. When the conversion is complete, the AD7942
enters the acquisition phase and powers down. Each ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK driving edges. The data is valid on
both SCK edges. Although the nondriving edge can be used to
capture the data, a digital host also using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when SDI goes high,
whichever is earlier, SDO returns to high impedance and
another AD7942 can be read.
If multiple AD7942s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CNV
CNV
CS2
CS1
CONVERT
DIGITAL HOST
SDI AD7942 SDO
SDI AD7942 SDO
SCK
SCK
DATA IN
CLK
Figure 34. CS Mode 4-Wire Without Busy Indicator Connection Diagram
CNV
ACQUISITION
t_CONV
CONVERSION
t_SSDICNV
SDI (CS1)
t_HSDICNV
t_CYC
t_ACQ
ACQUISITION
SDI (CS2)
SCK
SDO
t_SCKL
t_SCK
1
2
3
12
13
14
t_HSDO
t_EN
t_SCKH
t_DSDO
D13 D12 D11
D1 D0
15
16
D13 D12
26
27
28
t_DIS
D1 D0
Figure 35. CS Mode 4-Wire Without Busy Indicator, Serial Interface Timing
Rev. B | Page 19 of 24