AD5327_15 Datasheet, PDF (19/28 Pages) Analog Devices – 2.5 V to 5.5 V, 400 A, Quad Voltage Output, 8-/10-/12-Bit DACs in 16-Lead TSSOP

AD5307/AD5317/AD5327
The time to exit power-down is typically 2.5 μs for VDD = 5 V
and 5 μs when VDD = 3 V. This is the time from the rising edge
of PD to when the output voltage deviates from its power-down
voltage. See Figure 23 for a plot.
RESISTOR
STRING DAC
AMPLIFIER
V_OUT
POWER-DOWN
CIRCUITRY
Figure 36. Output Stage During Power-Down
MICROPROCESSOR INTERFACING
ADSP-2101/ADSP-2103-to-
AD5307/AD5317/AD5327 Interface
Figure 37 shows a serial interface between the AD5307/AD5317/
AD5327 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is
programmed through the SPORT control register and should be
configured as follows: internal clock operation, active low framing,
16-bit word length. Transmission is initiated by writing a word
to the Tx register after SPORT is enabled. The data is clocked
out on each rising edge of the DSP’s serial clock and clocked
into the AD5307/AD5317/AD5327 on the falling edge of the
DAC’s SCLK.
ADSP-2101/
ADSP-2103¹
TFS
DT
SCLK
AD5307/
AD5317/
AD5327¹
SYNC
DIN
SCLK
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 37. ADSP-2101/ADSP-2103-to-AD5307/AD5317/AD5327 Interface
68HC11/68L11-to-AD5307/AD5317/AD5327 Interface
Figure 38 shows a serial interface between the AD5307/AD5317/
AD5327 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5307/AD5317/
AD5327, and the MOSI output drives the serial data line (DIN)
of the DAC. The SYNC signal is derived from a port line (PC7).
The set-up conditions for correct operation of this interface are as
follows: The 68HC11/68L11 should be configured so that its CPOL
bit is 0 and its CPHA bit is 1. When data is being transmitted to the
DAC, the SYNC line is taken low (PC7). With this configuration,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes, with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to
the AD5307/AD5317/AD5327, PC7 is left low after the first
eight bits are transferred and a second serial write operation
is performed to the DAC. PC7 is taken high at the end of this
procedure.
68HC11/68L11¹
PC7
SCK
MOSI
AD5307/
AD5317/
AD5327¹
SYNC
SCLK
DIN
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 38. 68HC11/68L11-to-AD5307/AD5317/AD5327 Interface
80C51/80L51-to-AD5307/AD5317/AD5327 Interface
Figure 39 shows a serial interface between the AD5307/AD5317/
AD5327 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5307/AD5317/AD5327, and RxD drives the serial data
line of the part. The SYNC signal is again derived from a bit-
programmable pin on the port. In this case, Port Line P3.3 is
used. When data is to be transmitted to the AD5307/AD5317/
AD5327, P3.3 is taken low. The 80C51/80L51 transmits data only
in 8-bit bytes; therefore, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data LSB first. The AD5307/AD5317/AD5327 require
their data with the MSB as the first bit received. The
80C51/80L51 transmit routine should take this into account.
80C51/80L51¹
P3.3
TxD
RxD
AD5307/
AD5317/
AD5327¹
SYNC
SCLK
DIN
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 39. 80C51/80L51-to-AD5307/AD5317/AD5327 Interface
MICROWIRE-to-AD5307/AD5317/AD5327 Interface
Figure 40 shows an interface between the AD5307/AD5317/
AD5327 and a MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5307/AD5317/AD5327 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
MICROWIRE¹
CS
SK
SO
AD5307/
AD5317/
AD5327¹
SYNC
SCLK
DIN
1_{ADDITIONAL PINS OMITTED FOR CLARITY.}
Figure 40. MICROWIRE-to-AD5307/AD5317/AD5327 Interface
Rev. C | Page 19 of 28