ADSP-BF516BSWZ-4 Datasheet, PDF (18/68 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 7. Signal Descriptions
Signal Name
Type Function
Driver
Type¹
PF8/MDC/PPI D8/SPI1SEL4
I/O GPIO/Ethernet Management Channel Clock/PPI Data 8/SPI1 Slave Select 4
C
PF9/MDIO/PPI D9/TMR2
I/O GPIO/Ethernet Management Channel Serial Data/PPI Data 9/Timer 2
C
PF10/ETxD0/PPI D10/TMR3
I/O GPIO/Ethernet MII or RMII Transmit D0/PPI Data 10/Timer 3
C
PF11/ERxD0/PPI D11/PWM AH/TACI3
I/O GPIO/Ethernet MII Receive D0/PPI Data 11/PWM AH output
C
/Timer3 Alternate Capture Input
PF12/ETxD1/PPI D12/PWM AL
I/O GPIO/Ethernet MII Transmit D1/PPI Data 12/PWM AL Output
C
PF13/ERxD1/PPI D13/PWM BH
I/O GPIO/Ethernet MII or RMII Receive D1/PPI Data 13/PWM BH Output
C
PF14/ETxEN/PPI D14/PWM BL
I/O GPIO/Ethernet MII Transmit Enable/PPI Data 14/PWM BL Out
C
PF15²/RMII PHYINT/PPI D15/PWM_SYNCA I/O GPIO/Ethernet MII PHY Interrupt/PPI Data 15/Alternate PWM Sync
C
Port G: GPIO and Multiplexed Peripherals
PG0/MIICRS/RMIICRS/HWAIT ³/SPI1SEL3
I/O GPIO/Ethernet MII or RMII Carrier Sense or RMII Data Valid/HWAIT/SPI1 Slave Select3 C
PG1/ERxER/DMAR1/PWM CH
I/O GPIO/Ethernet MII or RMII Receive Error/DMA Req 1/PWM CH Out
C
PG2/MIITxCLK/RMIIREF_CLK/DMAR0/PWM CL I/O GPIO/Ethernet MII or RMII Reference Clock/DMA Req 0/PWM CL Out
C
PG3/DR0PRI/RSI_DATA0/SPI0SEL5/TACLK3 I/O GPIO/SPORT0 Primary Rx Data/RSI Data 0/SPI0 Slave Select 5/Timer3 Alternate CLK C
PG4/RSCLK0/RSI_DATA1/TMR5/TACI5
I/O GPIO/SPORT0 Rx Clock/RSI Data 1/Timer 5/Timer5 Alternate Capture Input
D
PG5/RFS0/RSI_DATA2/PPICLK/TMRCLK
I/O GPIO/SPORT0 Rx Frame Sync/RSI Data 2/PPI Clock/External Timer Reference
C
PG6/TFS0/RSI_DATA3/TMR0/PPIFS1
I/O GPIO/SPORT0 Tx Frame Sync/RSI Data 3/Timer0/PPI Frame Sync1
C
PG7/DT0PRI/RSI_CMD/TMR1/PPIFS2
I/O GPIO/SPORT0 Tx Primary Data/RSI Command/Timer 1/PPI Frame Sync2
C
PG8/TSCLK0/RSI_CLK/TMR6/TACI6
I/O GPIO/SPORT0 Tx Clock/RSI Clock/Timer 6/Timer6 Alternate Capture Input
D
PG9/DT0SEC/UART0TX/TMR4
I/O GPIO/SPORT0 Secondary Tx Data/UART0 Transmit/Timer 4
C
PG10/DR0SEC/UART0RX/TACI4
I/O GPIO/SPORT0 Secondary Rx Data/UART0 Receive/Timer4 Alternate Capture Input C
PG11/SPI0SS/AMS2/SPI1SEL5/TACLK2
I/O GPIO/SPI0 Slave Device Select/Asynchronous Memory Bank Select 2/SPI1 Slave C
Select 5/Timer2 Alternate CLK
PG12/SPI0SCK/PPICLK/TMRCLK/PTP_PPS I/O GPIO/SPI0 Clock/PPI Clock/External Timer Reference/PTP Pulse Per Second Out D
PG13/SPI0MISO⁴/TMR0/PPIFS1/
PTP_CLKOUT
I/O GPIO/SPI0 Master In Slave Out/Timer0/PPI Frame Sync1/PTP Clock Out
C
PG14/SPI0MOSI/TMR1/PPIFS2/PWM TRIP
/PTP_AUXIN
I/O GPIO/SPI0 Master Out Slave In/Timer 1/PPI Frame Sync2/PWM Trip/PTP Auxiliary C
Snapshot Trigger Input
PG15/SPI0SEL2/PPIFS3/AMS3
I/O GPIO/SPI0 Slave Select 2/PPI Frame Sync3/Asynchronous Memory Bank Select 3 C
Port H: GPIO and Multiplexed Peripherals
PH0/DR1PRI/SPI1SS/RSI_DATA4
I/O GPIO/SPORT1 Primary Rx Data/SPI1 Device Select/RSI Data 4
C
PH1/RFS1/SPI1MISO/RSI_DATA5
I/O GPIO/SPORT1 Rx Frame Sync/SPI1 Master In Slave Out/RSI Data 5
C
PH2/RSCLK1/SPI1SCK/RSI DATA6
I/O GPIO/SPORT1 Rx Clock/SPI1 Clock/RSI Data 6
D
PH3/DT1PRI/SPI1MOSI/RSI DATA7
I/O GPIO/SPORT1 Primary Tx Data/SPI1 Master Out Slave In/RSI Data 7
C
PH4/TFS1/AOE/SPI0SEL3/CUD
I/O GPIO/SPORT1 Tx Frame Sync/Asynchronous Memory Output Enable/SPI0 Slave C
Select 3/Counter Up Direction
PH5/TSCLK1/ARDY/PTP_EXT_CLKIN/CDG I/O GPIO/SPORT1 Tx Clock/Asynchronous Memory Hardware Ready Control/
D
External Clock for PTP TSYNC/Counter Down Gate
PH6/DT1SEC/UART1TX/SPI1SEL1/CZM
I/O GPIO/SPORT1 Secondary Tx Data/UART1 Transmit/SPI1 Slave Select 1
C
/Counter Zero Marker
PH7/DR1SEC/UART1RX/TMR7/TACI2
I/O GPIO/SPORT1 Secondary Rx Data/UART1 Receive/Timer 7/Timer2 Alternate Clock C
Input
Rev. B | Page 18 of 68 | January 2011