ADE7756_15 Datasheet, PDF (18/32 Pages) Analog Devices – Active Energy Metering IC with Serial Interface

ADE7756
CHANNEL 1 ADC
Figure 18 shows the ADC and signal processing chain for Chan-
nel 1. In waveform sampling mode the ADC outputs a signed
the expression that shows how the gain adjustment is related to
the contents of the Active Power Gain register.
two’s complement 20-bit data word at a maximum of 27.9 kSPS
(CLKIN/128). The output of the ADC can be scaled by ± 50% to
perform an overall power calibration or to calibrate the ADC out-
put. While the ADC outputs a 20-bit two’s complement value, the
maximum full-scale positive value from the ADC is limited to
40000h (+262,144 decimal). The maximum full-scale negative
value is limited to C0000h (–262,144 Decimal). If the analog
inputs are overranged, the ADC output code will clamp at these
Code
=

 ^ADC
×
_{1 +}

APGAIN
2¹²


For example when 7FFh is written to the Active Power Gain
register the ADC output is scaled up by 50%. 7FFh = 2047 deci-
mal, 2047/2¹² = 0.5. Similarly, 801h = –2047 decimal (signed
two’s complement) and ADC output is scaled by –50%. These
two examples are graphically illustrated in Figure 18.
values. With the specified full scale analog input signal of 1 V (or
Channel 1 Sampling
0.5 V or 0.25 V—see Analog Inputs section) the ADC will produce _{The waveform samples may also be routed to the Waveform}
an output code which is approximately 63% of its full-scale value.
This is illustrated in Figure 18. The diagram in Figure 15 shows
a full-scale voltage signal being applied to the differential inputs
V1P and V1N. The ADC output swings between D7AE1h
(–165,151) and 2851Fh (+165,151). This is approximately 63%
of the full-scale value 40000h (262,144). Overranging the analog
E _{inputs with more than 1 V differential (0.5 or 0.25, depending}
on Channel 1 full-scale selection) will cause the ADC output to
increase towards its full-scale value. However for specified opera-
T ^{tion the differential signal on the analog inputs should not exceed}
the recommended value of 1.0 V.
Channel 1 ADC Gain Adjust
The ADC gain in Channel 1 can be adjusted by using the multi-
E _{plier and Active Power Gain register (APGAIN[11:0]). The}
gain of the ADC is adjusted by writing a two’s complement
12-bit word to the Active Power Gain register. Following is
register (MODE[14:13] = 1, 0) to be read by the system master
(MCU). In waveform sampling mode the WSMP bit (Bit 3) in
the Interrupt Enable register must also be set to Logic 1. The
Active Power and Energy calculation will remain uninterrupted
during waveform sampling.
When in waveform sample mode, one of four output sample rates
may be chosen by using Bits 11 and 12 of the Mode register
(WAVSEL1, 0). The output sample rate may be 27.9 kSPS,
14 kSPS, 7 kSPS or 3.5 kSPS—see Mode Register section. The
interrupt request output IRQ signals a new sample availability
by going active low. The timing is shown in Figure 19. The
20-bit waveform samples are transferred from the ADE7756 one
byte (8 bits) at a time, with the most significant byte shifted out
first. The 20-bit data word is right-justified and sign extended
to 24 bits (three bytes)—see Serial Interface section.
L _{x1, x2, x4,}
x8, x16
O _GAIN[2:0]
V1P
V1
V1N
PGA1
S _{1V, 0.5V, 0.25V, 125mV,}
62.5mV, 31.3mV, 15.6mV
0V
B_{ANALOG INPUT}
O^RANGE
2.42V, 1.21V, 0.6V
GAIN[4:3]
REFERENCE
DIGITAL
MULTIPLIER LPF
ADC
1
1 ^SINC3 20
12
HPF
TO
WAVEFORM
REGISTER
WAVEFORM[23:0]
TO
MULTIPLIER
801Hex – 7FFHex
CHANNEL 1 (ACTIVE POWER)
CALIBRATION RANGE
APGAIN[11:0]
40000h
2851Fh
+FS
+63% FS
00000h
D7AE1h
C0000h
–63% FS
–FS
ADC OUTPUT
WORD RANGE
3C7AEh
2851Fh
1428Fh
00000h
EBD71h
D7AE1h
C3852h
+94.5% FS
+63% FS
+31.5% FS
–31.5% FS
–63% FS
–94.5% FS
000h 7FFh 801h
APGAIN[11:0]
Figure 18. ADC and Signal Processing in Channel 1
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