AD9910_07 Datasheet, PDF (18/60 Pages) Analog Devices – 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer

AD9910
DIGITAL RAMP MODULATION MODE
In digital ramp modulation mode (Figure 24), the modulated
DDS signal control parameter is supplied directly from the
digital ramp generator (DRG). The ramp generation parameters
are controlled through the serial I/O port.
The ramp generation parameters allow the user to control both
the rising and falling slopes of the ramp. The upper and lower
boundaries of the ramp, the step size and step rate of the rising
portion of the ramp, and the step size and step rate of the falling
portion of the ramp are all programmable.
The ramp is digitally generated with 32-bit output resolution.
The 32-bit output of the DRG can be programmed to represent
frequency, phase, or amplitude. When programmed to represent
frequency, all 32 bits are used. However, when programmed to
represent phase or amplitude, only the 16 MSBs or 14 MSBs,
respectively, are used.
The ramp direction (rising or falling) is externally controlled by
the DRCTL pin. An additional pin (DRHOLD) allows the user
to suspend the ramp generator in its present state.
RAM_SWP_OVR
2
SDIO
SCLK
I/O_RESET
RAM
CS
OSK
OUTPUT
SHIFT
KEYING
DRCTL ²
DRHOLD
DROVER
DIGITAL
RAMP
GENERATOR
PROFILE
I/O_UPDATE
3
PROGRAMMING
REGISTERS
8
16
DAC FSC
PARALLEL
INPUT
2
AD9910
DDS
8
DAC FSC
AUX
DAC
8-BIT
AMPLITUDE (A)
PHASE (θ)
DATA
ROUTE FREQUENCY (ω)
AND
PARTITION
CONTROL
A
θ
ω
CLOCK
Acos (ωt+θ)
Asin (ωt+θ)
INVERSE
SINC
FILTER
SYSCLK
÷2
DAC
14-BIT
INTERNAL CLOCK TIMING
AND CONTROL
PLL
DAC_RSET
IOUT
IOUT
REFCLK_OUT
REF_CLK
REF_CLK
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
POWER
DOWN
CONTROL
MULTICHIP
SYNCHRONIZATION
2
2
XTAL_SEL
Figure 24. Digital Ramp Modulation Mode
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