AD8139_07 Datasheet, PDF (18/24 Pages) Analog Devices – Low Noise, Rail-to-Rail, Differential ADC Driver

AD8139
THEORY OF OPERATION
The AD8139 is a high speed, low noise differential amplifier
fabricated on the Analog Devices second-generation eXtra Fast
Complementary Bipolar (XFCB) process. It is designed to
provide two closely balanced differential outputs in response to
either differential or single-ended input signals. Differential
gain is set by external resistors, similar to traditional voltage-
feedback operational amplifiers. The common-mode level of
the output voltage is set by a voltage at the VOCM pin and is
independent of the input common-mode voltage. The AD8139
has an H-bridge input stage for high slew rate, low noise, and
low distortion operation and rail-to-rail output stages that
provide maximum dynamic output range. This set of features
allows for convenient single-ended-to-differential conversion, a
common need to take advantage of modern high resolution
ADCs with differential inputs.
TYPICAL CONNECTION AND DEFINITION OF
TERMS
Figure 59 shows a typical connection for the AD8139, using
matched external RF/RG networks. The differential input
terminals of the AD8139, VAP and VAN, are used as summing
junctions. An external reference voltage applied to the VOCM
terminal sets the output common-mode voltage. The two
output terminals, VOP and VON, move in opposite directions in a
balanced fashion in response to an input signal.
C_F
V_IP
R_G
V_OCM
R_G
V_IN
R_F
V_AP
+
V_ON
AD8139
V_{AN –}
V_OP
–
R_{L, dm} V_{O, dm}
+
R_F
C_F
Figure 59. Typical Connection
The differential output voltage is defined as
VO, dm = VOP − VON
(1)
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
V_{O, cm} =
V_OP + V_ON
2
(2)
Output Balance
Output balance is a measure of how well VOP and VON are
matched in amplitude and how precisely they are 180° out of
phase with each other. It is the internal common-mode feedback
loop that forces the signal component of the output common-mode
towards zero, resulting in the near perfectly balanced differential
outputs of identical amplitude and exactly 180° out of phase. The
output balance performance does not require tightly matched
external components, nor does it require that the feedback factors
of each loop be equal to each other. Low frequency output balance
is limited ultimately by the mismatch of an on-chip voltage divider,
which is trimmed for optimum performance.
Output balance is measured by placing a well-matched resistor
divider across the differential voltage outputs and comparing
the signal at the midpoint of the divider with the magnitude of
the differential output. By this definition, output balance is
equal to the magnitude of the change in output common-mode
voltage divided by the magnitude of the change in output
differential-mode voltage:
Output Balance = ^{ΔVO, cm}
(3)
ΔV_{O, dm}
The block diagram of the AD8139 in Figure 60 shows the
external differential feedback loop (RF/RG networks and the
differential input transconductance amplifier, GDIFF) and the
internal common-mode feedback loop (voltage divider across
VOP and VON and the common-mode input transconductance
amplifier, GCM). The differential negative feedback drives the
voltages at the summing junctions VAN and VAP to be essentially
equal to each other.
VAN = VAP
(4)
The common-mode feedback loop drives the output common-
mode voltage, sampled at the midpoint of the two 500 Ω resistors,
to equal the voltage set at the VOCM terminal. This ensures that
V_OP
= V_OCM
+
V_{O, dm}
2
(5)
and
V_ON
= V_OCM
− ^{VO, dm}
2
R_G
V_IN
(6)
R_F
10pF
+
V_AN
V_AP
G_DIFF
G_O
MIDSUPPLY
G_CM
500Ω
V_OP
500Ω
V_OCM
V_IP
R_G
G_O
V_ON
+
10pF
R_F
Figure 60. Block Diagram
Rev. B | Page 18 of 24