AD7985_17 Datasheet, PDF (18/29 Pages) Analog Devices – 16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP

Data Sheet
DIGITAL INTERFACE
Although the AD7985 has a reduced number of pins, it offers
flexibility in the serial interface modes.
In CS mode, the AD7985 is compatible with SPI, MICROWIRE,
QSPI, and digital hosts. In CS mode, the AD7985 can use either a
3-wire or a 4-wire interface. A 3-wire interface that uses the CNV,
SCK, and SDO signals minimizes wiring connections, which is
useful, for example, in isolated applications. A 4-wire interface
that uses the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.
In chain mode, the AD7985 provides a daisy-chain feature that
uses the SDI input for cascading multiple ADCs on a single data
line similar to a shift register. Chain mode is available only in
normal mode (TURBO is low).
The mode in which the device operates depends on the SDI
level when the CNV rising edge occurs. CS mode is selected if
SDI is high, and chain mode is selected if SDI is low. The SDI
hold time is such that when SDI and CNV are connected
together, chain mode is always selected.
In normal mode operation, the AD7985 offers the option of
forcing a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
AD7985
The busy indicator feature is enabled in CS mode if CNV or
SDI is low when the ADC conversion ends (see Figure 29 and
Figure 33). TURBO must be kept low for both digital interfaces.
When CNV is low, readback can occur during conversion or
acquisition, or it can be split across acquisition and conversion,
as described in the following sections.
A discontinuous SCK is recommended because the device is
selected with CNV low, and SCK activity begins to clock out data.
Note that in the following sections, the timing diagrams indicate
digital activity (SCK, CNV, SDI, and SDO) during the conversion.
However, due to the possibility of performance degradation, digi-
tal activity must occur only prior to the safe data reading time,
tDATA, because the AD7985 provides error correction circuitry
that can correct for an incorrect bit decision during this time.
From tDATA to tCONV, there is no error correction, and conversion
results may be corrupted.
Similarly, tQUIET, the time from the last falling edge of SCK to
the rising edge of CNV, must remain free of digital activity.
The user must configure the AD7985 and initiate the busy
indicator (if desired in normal mode) prior to tDATA.
It is also possible to corrupt the sample by having SCK near the
sampling instant. Therefore, it is recommended that the digital
pins be kept quiet for approximately 20 ns before and 10 ns after
the rising edge of CNV, using a discontinuous SCK whenever
possible to avoid any potential performance degradation.
Rev. C | Page 17 of 28