AD7763 Datasheet, PDF (18/32 Pages) Analog Devices – 24-Bit, 625 kSPS, 109 dB Σ-Δ ADC with On-Chip Buffers, Serial Interface

AD7763
READING DATA USING THE I²S INTERFACE
The AD7763 has the capability of operating using an I²S
interface. The interface is functional only for the output of
stereo data and does not apply to writing to control registers,
programming coefficients for the digital filter, or the reading of
any information contained in the AD7763 onboard registers.
All of these operations must be undertaken using the normal
serial interface.
The I²S interface operates using two AD7763 devices. The pins
shown in Table 9 are used as the output pins for the SCK (serial
clock), SD (serial data), and WS (word select) signals for the I²S
interface.
Table 9.
SPI Pins
I²S Signals
FSO
WS
SDO
SD
SCO
SCK
To enable the I²S interface, the I²S pin is set to logic high. The
Share Pins SH[2:0] of both AD7763 devices that use the I²S
interface are set to 001. The Address Pins ADR[2:0] of the two
devices must also be set to 000 and 001, respectively.
The WS and SCK signals that are used for the interface can be
taken from either AD7763 device. Note that the device that is
assigned Address 000 is defined as the left channel, and its data
is output on the SD line when WS is logic low.
The WS and SCK signals can be taken from the appropriate
pins on either of the AD7763 devices using the I²S interface.
The SD pins of both devices must be connected together, as
shown in Figure 27.
Data is clocked out on the SD line in accordance with Figure 28.
Because Device A is assigned Address 000, it is defined as the
left channel. The 32-bit conversion result from the left channel
is clocked out when WS is logic low, with the MSB being clocked
out first. Each 32-bit result consists of 24 data bits in twos
complement format, followed by eight status bits, as shown in
the following bit map.
D7
D6 D5
D4 D3
D2 D1 D0
DVALID OVR UFILTER LPWR FILTER_OK ADR0 0 Three-
State
DEVICE
ADDRESS
000
1
SH[2:0]
001
MCLK
LEFT CHANNEL
AD7763
(000)
ADR[2:0]
FSO
I²S
A SCO
SH[2:0]
SDO
MCLK
WS
SCK
3-WIRE
I²S INTERFACE
SD
MCLK
SH[2:0]
SDO
1
DEVICE
ADDRESS
001
I²S
B
ADR[2:0]
AD7763
(001)
RIGHT CHANNEL
Figure 27. Two AD7763 Devices Operating Using the I²S Interface
Conversion results from Device B, assigned Address 001, are
clocked out on the SD line when WS is logic high. The SD line
goes into three-state on the falling edge of the 32nd SCK after
the falling edge of WS (left channel data) and also on the falling
edge of the 32nd SCK after the rising edge of WS (right channel
data). This permits swapping of the SD bus between the left and
right channel devices without contention.
In decimate × 32 mode the I²S interface is operational only
when CDIV = 0 and SCR = 1. The interface operates for all
combinations of SCR and CDIV in all other modes of
decimation.
The DRDY pulse still operates as in the normal serial SPI-type
interface, pulsing low immediately prior to the falling edge of
WS but having no meaning in the I²S interface specification.
SCK A (O)
WS A (O)
SD (O)
THREE-
STATE
D23
D22
D21
ST2
ST1
THREE-
STATE
D23
D22
D21
ST2
ST1
THREE-
STATE
RIGHT CHANNEL
DEVICE B
(WORD n – 1)
LEFT CHANNEL
DEVICE A
(WORD n)
RIGHT CHANNEL
DEVICE B
(WORD n + 1)
LEFT CHANNEL
DEVICE A
(WORD n + 2)
Figure 28. Timing Diagram for I²S Interface
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